 | 2011 |
| 44 |  | Fengwei An,
Hans Jürgen Mattausch,
Tetsushi Koide:
Real-time hybrid learning and recognition system with software-hardware cooperation.
ROBIO 2011: 2505-2510 |
| 43 |  | Ali Ahmadi,
Hans Jürgen Mattausch,
Md. Anwarul Abedin,
Mahmoud Saeidi,
Tetsushi Koide:
An associative memory-based learning model with an efficient hardware implementation in FPGA.
Expert Syst. Appl. 38(4): 3499-3513 (2011) |
| 42 |  | Norio Sadachika,
Shu Mimura,
Akihiro Yumisaki,
Koh Johguchi,
Akihiro Kaya,
Mitiko Miura-Mattausch,
Hans Jürgen Mattausch:
Prediction of Circuit-Performance Variations from Technology Variations for Reliable 100 nm SOC Circuit Design.
IEICE Transactions 94-C(3): 361-367 (2011) |
| 41 |  | Takeshi Kumaki,
Tetsushi Koide,
Hans Jürgen Mattausch,
Masaharu Tagami,
Masakatsu Ishizaki:
Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems.
IEICE Transactions 94-D(9): 1742-1754 (2011) |
| 40 |  | Takashi Kurafuji,
Masaru Haraguchi,
Masami Nakajima,
Tetsu Nishijima,
Tetsushi Tanizaki,
Hiroyuki Yamasaki,
Takeaki Sugimura,
Yuta Imai,
Masakatsu Ishizaki,
Takeshi Kumaki,
Kan Murata,
Kanako Yoshida,
Eisuke Shimomura,
Hideyuki Noda,
Yoshihiro Okuno,
Shunsuke Kamijo,
Tetsushi Koide,
Hans Jürgen Mattausch,
Kazutami Arimoto:
A Scalable Massively Parallel Processor for Real-Time Image Processing.
J. Solid-State Circuits 46(10): 2363-2373 (2011) |
| 2010 |
| 39 |  | Tetsushi Koide,
R. Kimura,
T. Sugahara,
K. Okazaki,
Hans Jürgen Mattausch:
Architecture and FPGA-Implementation of Scalable Picture Segmentation by 2D Scanning with Flexible Pixel-Block Size.
ICNC 2010: 128-132 |
| 38 |  | Akio Kawabata,
Tetsushi Koide,
Hans Jürgen Mattausch:
Optimization Vector Quantization by Adaptive Associative-Memory-Based Codebook Learning in Combination with Huffman Coding.
ICNC 2010: 15-19 |
| 37 |  | Takashi Kurafuji,
Masaru Haraguchi,
Masami Nakajima,
Takayuki Gyohten,
Tetsu Nishijima,
Hiroyuki Yamasaki,
Yuta Imai,
Masakatsu Ishizaki,
Takeshi Kumaki,
Yoshihiro Okuno,
Tetsushi Koide,
Hans Jürgen Mattausch,
Kazutami Arimoto:
A scalable massively parallel processor for real-time image processing.
ISSCC 2010: 334-335 |
| 36 |  | Koh Johguchi,
Akihiro Kaya,
Shinya Izumi,
Hans Jürgen Mattausch,
Tetsushi Koide,
Norio Sadachika:
Measurement-Based Ring Oscillator Variation Analysis.
IEEE Design & Test of Computers 27(5): 6-13 (2010) |
| 2009 |
| 35 |  | Masataka Miyake,
Daisuke Hori,
Norio Sadachika,
Uwe Feldmann,
Mitiko Miura-Mattausch,
Hans Jürgen Mattausch,
Takahiro Iizuka,
Kazuya Matsuzawa,
Yasuyuki Sahara,
Teruhiko Hoshida,
Toshiro Tsukada:
Non-Quasi-Static Carrier Dynamics of MOSFETs under Low-Voltage Operation.
IEICE Transactions 92-C(5): 608-615 (2009) |
| 34 |  | Masataka Miyake,
Daisuke Hori,
Norio Sadachika,
Uwe Feldmann,
Mitiko Miura-Mattausch,
Hans Jürgen Mattausch,
Tatsuya Ohguro,
Takahiro Iizuka,
Masahiko Taguchi,
Shunsuke Miyamoto:
Degraded Frequency-Tuning Range and Oscillation Amplitude of LC-VCOs due to the Nonquasi-Static Effect in MOS Varactors.
IEICE Transactions 92-C(6): 777-784 (2009) |
| 2008 |
| 33 |  | Norio Sadachika,
Takahiro Murakami,
Hideki Oka,
Ryou Tanabe,
Hans Jürgen Mattausch,
Mitiko Miura-Mattausch:
Compact Double-Gate Metal-Oxide-Semiconductor Field Effect Transistor Model for Device/Circuit Optimization.
IEICE Transactions 91-C(8): 1379-1381 (2008) |
| 32 |  | Takeshi Kumaki,
Masakatsu Ishizaki,
Tetsushi Koide,
Hans Jürgen Mattausch,
Yasuto Kuroda,
Takayuki Gyohten,
Hideyuki Noda,
Katsumi Dosaka,
Kazutami Arimoto,
Kazunori Saito:
Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor.
IEICE Transactions 91-C(9): 1409-1418 (2008) |
| 31 |  | Tatsuya Ezaki,
Dondee Navarro,
Youichi Takeda,
Norio Sadachika,
G. Suzuki,
Mitiko Miura-Mattausch,
Hans Jürgen Mattausch,
Tatsuya Ohguro,
Takahiro Iizuka,
Masahiko Taguchi,
Shigetaka Kumashiro,
Shunsuke Miyamoto:
Non-quasi-static approach with surface-potential-based MOSFET model HiSIM for RF circuit simulations.
Mathematics and Computers in Simulation 79(4): 1096-1106 (2008) |
| 2007 |
| 30 |  | Takeshi Kumaki,
Tetsushi Koide,
Hans Jürgen Mattausch,
Yasuto Kuroda,
Hideyuki Noda,
Katsumi Dosaka,
Kazutami Arimoto,
Kazunori Saito:
Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine.
ISCAS 2007: 525-528 |
| 29 |  | Md. Anwarul Abedin,
Yuki Tanaka,
Ali Ahmadi,
Shogo Sakakibara,
Tetsushi Koide,
Hans Jürgen Mattausch:
Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories.
IEICE Transactions 90-A(6): 1240-1243 (2007) |
| 28 |  | Koh Johguchi,
Hans Jürgen Mattausch,
Tetsushi Koide,
Tetsuo Hironaka:
4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words.
IEICE Transactions 90-C(11): 2157-2160 (2007) |
| 27 |  | Takeshi Kumaki,
Yasuto Kuroda,
Masakatsu Ishizaki,
Tetsushi Koide,
Hans Jürgen Mattausch,
Hideyuki Noda,
Katsumi Dosaka,
Kazutami Arimoto,
Kazunori Saito:
Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer.
IEICE Transactions 90-D(1): 334-345 (2007) |
| 26 |  | Takeshi Kumaki,
Yutaka Kono,
Masakatsu Ishizaki,
Tetsushi Koide,
Hans Jürgen Mattausch:
Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory.
IEICE Transactions 90-D(1): 346-354 (2007) |
| 25 |  | Takeshi Kumaki,
Masakatsu Ishizaki,
Tetsushi Koide,
Hans Jürgen Mattausch,
Yasuto Kuroda,
Hideyuki Noda,
Katsumi Dosaka,
Kazutami Arimoto,
Kazunori Saito:
Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor.
IEICE Transactions 90-D(8): 1312-1315 (2007) |
| 2006 |
| 24 |  | Koh Johguchi,
Zhaomin Zhu,
Hans Jürgen Mattausch,
Tetsushi Koide,
Tetsuo Hironaka,
Kazuya Tanigawa:
Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline.
APCCAS 2006: 1297-1300 |
| 23 |  | Md. Anwarul Abedin,
Yuki Tanaka,
Ali Ahmadi,
Tetsushi Koide,
Hans Jürgen Mattausch:
Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search.
APCCAS 2006: 1309-1312 |
| 22 |  | Takeshi Kumaki,
Y. Kouno,
Masakatsu Ishizaki,
Tetsushi Koide,
Hans Jürgen Mattausch:
Application of Multi-ported CAM for Parallel Coding.
APCCAS 2006: 1859-1862 |
| 21 |  | Takashi Morimoto,
Hidekazu Adachi,
K. Yamaoka,
K. Awane,
Tetsushi Koide,
Hans Jürgen Mattausch:
An FPGA-Based Region-Growing Video Segmentation System with Boundary-Scan-Only LSI Architecture.
APCCAS 2006: 944-947 |
| 20 |  | K. Yamaoka,
Takashi Morimoto,
Hidekazu Adachi,
Tetsushi Koide,
Hans Jürgen Mattausch:
Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking.
ASP-DAC 2006: 176-181 |
| 19 |  | K. Yamaoka,
Takashi Morimoto,
Hidekazu Adachi,
K. Awane,
Tetsushi Koide,
Hans Jürgen Mattausch:
Multi-object tracking VLSI architecture using image-scan based region growing and feature matching.
ISCAS 2006 |
| 18 |  | Hideyuki Noda,
Katsumi Dosaka,
Hans Jürgen Mattausch,
Tetsushi Koide,
Fukashi Morishita,
Kazutami Arimoto:
A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC.
IEICE Transactions 89-C(11): 1612-1619 (2006) |
| 17 |  | Takashi Morimoto,
Hidekazu Adachi,
Osamu Kiriyama,
Tetsushi Koide,
Hans Jürgen Mattausch:
Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video-Segmentation.
IEICE Transactions 89-D(3): 1299-1302 (2006) |
| 2005 |
| 16 |  | Takashi Morimoto,
Osamu Kiriyama,
Hidekazu Adachi,
Zhaomin Zhu,
Tetsushi Koide,
Hans Jürgen Mattausch:
A low-power video segmentation LSI with boundary-active-only architecture.
ASP-DAC 2005: 13-14 |
| 15 |  | Ali Ahmadi,
Md. Anwarul Abedin,
Hans Jürgen Mattausch,
Tetsushi Koide:
A parallel hardware design for parametric active contour models.
AVSS 2005: 609-613 |
| 14 |  | Takashi Morimoto,
Osamu Kiriyama,
Yohmei Harada,
Hidekazu Adachi,
Tetsushi Koide,
Hans Jürgen Mattausch:
Object tracking in video pictures based on image segmentation and pattern matching.
ISCAS (4) 2005: 3215-3218 |
| 13 |  | T. Saito,
M. Maeda,
Tetsuo Hironaka,
Kazuya Tanigawa,
Tetsuya Sueyoshi,
K. Aoyama,
Tetsushi Koide,
Hans Jürgen Mattausch:
Design of superscalar processor with multi-bank register file.
ISCAS (4) 2005: 3507-3510 |
| 12 |  | Takeshi Kumaki,
Yasuto Kuroda,
Tetsushi Koide,
Hans Jürgen Mattausch,
Hideyuki Noda,
Katsumi Dosaka,
Kazutami Arimoto,
Kazunori Saito:
CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example].
ISCAS (5) 2005: 5202-5205 |
| 11 |  | Shizunori Matsumoto,
Hiroaki Ueno,
Satoshi Hosokawa,
Toshihiko Kitamura,
Mitiko Miura-Mattausch,
Hans Jürgen Mattausch,
Tatsuya Ohguro,
Shigetaka Kumashiro,
Tetsuya Yamaguchi,
Kyoji Yamashita,
Noriaki Nakayama:
1/f-Noise Characteristics in 100 nm-MOSFETs and Its Modeling for Circuit Simulation.
IEICE Transactions 88-C(2): 247-254 (2005) |
| 10 |  | Hideyuki Noda,
Kazunari Inoue,
Hans Jürgen Mattausch,
Tetsushi Koide,
Katsumi Dosaka,
Kazutami Arimoto,
Kazuyasu Fujishima,
Kenji Anami,
Tsutomu Yoshihara:
Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh.
IEICE Transactions 88-C(4): 622-629 (2005) |
| 9 |  | Dondee Navarro,
Takeshi Mizoguchi,
Masami Suetake,
Kazuya Hisamitsu,
Hiroaki Ueno,
Mitiko Miura-Mattausch,
Hans Jürgen Mattausch,
Shigetaka Kumashiro,
Tetsuya Yamaguchi,
Kyoji Yamashita,
Noriaki Nakayama:
A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential.
IEICE Transactions 88-C(5): 1079-1086 (2005) |
| 8 |  | Kazunari Inoue,
Hideyuki Noda,
Kazutami Arimoto,
Hans Jürgen Mattausch,
Tetsushi Koide:
A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features.
IEICE Transactions 88-C(6): 1332-1342 (2005) |
| 7 |  | Takahiro Sasaki,
Tomohiro Inoue,
Nobuhiko Omori,
Tetsuo Hironaka,
Hans Jürgen Mattausch,
Tetsushi Koide:
Chip size and performance evaluations of shared cache for on-chip multiprocessor.
Systems and Computers in Japan 36(9): 1-13 (2005) |
| 2004 |
| 6 |  | Takashi Morimoto,
Yohmei Harada,
Tetsushi Koide,
Hans Jürgen Mattausch:
350nm CMOS test-chip for architecture verification of real-time QVGA color-video segmentation at the 90nm technology node.
ASP-DAC 2004: 531-532 |
| 5 |  | Yuji Yano,
Tetsushi Koide,
Hans Jürgen Mattausch:
Associative memory with fully parallel nearest-Manhattan-distance search for low-power real-time single-chip applications.
ASP-DAC 2004: 543-544 |
| 4 |  | Tetsuya Sueyoshi,
Hiroshi Uchida,
Hans Jürgen Mattausch,
Tetsushi Koide,
Yosuke Mitani,
Tetsuo Hironaka:
Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processors.
ASP-DAC 2004: 551-552 |
| 3 |  | Takashi Morimoto,
Yohmei Harada,
Tetsushi Koide,
Hans Jürgen Mattausch:
Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation.
IEICE Transactions 87-D(2): 500-503 (2004) |
| 2001 |
| 2 |  | D. Miyawaki,
Shizunori Matsumoto,
Hans Jürgen Mattausch,
S. Ooshiro,
Masami Suetake,
Michiko Miura-Mattausch,
Shigetaka Kumashiro,
Tetsuya Yamaguchi,
Kyoji Yamashita,
Noriaki Nakayama:
Correlation method of circuit-performance and technology fluctuations for improved design reliability.
ASP-DAC 2001: 39-44 |
| 2000 |
| 1 |  | Masayasu Tanaka,
N. Tokida,
T. Okagaki,
Michiko Miura-Mattausch,
Walter Hansch,
Hans Jürgen Mattausch:
High performance of short-channel MOSFETs due to an elevated central-channel doping.
ASP-DAC 2000: 365-370 |