 | 2012 |
| 15 |  | Laurent Sauvage,
Sylvain Guilley,
Florent Flament,
Jean-Luc Danger,
Yves Mathieu:
Blind Cartography for Side Channel Attacks: Cross-Correlation Cartography.
Int. J. Reconfig. Comp. 2012: (2012) |
| 14 |  | Stéphane Mancini,
Zahir Larabi,
Yves Mathieu,
Tomasz Toczek,
Lionel Pierrefeu:
Exploration of 3D grid caching strategies for ray-shooting.
J. Real-Time Image Processing 7(1): 3-19 (2012) |
| 2010 |
| 13 |  | Laurent Sauvage,
Sylvain Guilley,
Florent Flament,
Jean-Luc Danger,
Yves Mathieu:
Cross-Correlation Cartography.
ReConFig 2010: 268-273 |
| 12 |  | Laurent Sauvage,
Maxime Nassar,
Sylvain Guilley,
Florent Flament,
Jean-Luc Danger,
Yves Mathieu:
Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics.
Int. J. Reconfig. Comp. 2010: (2010) |
| 2009 |
| 11 |  | Laurent Sauvage,
Sylvain Guilley,
Jean-Luc Danger,
Yves Mathieu,
Maxime Nassar:
Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints.
DATE 2009: 640-645 |
| 10 |  | Zahir Larabi,
Yves Mathieu,
Stéphane Mancini:
High Efficiency Reconfigurable Cache for Image Processing.
ERSA 2009: 226-232 |
| 9 |  | Zahir Larabi,
Yves Mathieu,
Stéphane Mancini:
Efficient Data Access Management for FPGA-Based Image Processing SoCs.
IEEE International Workshop on Rapid System Prototyping 2009: 159-165 |
| 8 |  | Shivam Bhasin,
Jean-Luc Danger,
Florent Flament,
Tarik Graba,
Sylvain Guilley,
Yves Mathieu,
Maxime Nassar,
Laurent Sauvage,
Nidhal Selmane:
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow.
ReConFig 2009: 213-218 |
| 7 |  | Laurent Sauvage,
Maxime Nassar,
Sylvain Guilley,
Florent Flament,
Jean-Luc Danger,
Yves Mathieu:
DPL on Stratix II FPGA: What to Expect?.
ReConFig 2009: 243-248 |
| 6 |  | Laurent Sauvage,
Sylvain Guilley,
Yves Mathieu:
Electromagnetic Radiations of FPGAs: High Spatial Resolution Cartography and Attack on a Cryptographic Module.
TRETS 2(1): (2009) |
| 2008 |
| 5 |  | Sylvain Guilley,
Laurent Sauvage,
Jean-Luc Danger,
Tarik Graba,
Yves Mathieu:
Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs.
SSIRI 2008: 16-23 |
| 2007 |
| 4 |  | Sylvain Guilley,
Florent Flament,
Philippe Hoogvorst,
Renaud Pacalet,
Yves Mathieu:
Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors.
IEEE Design & Test of Computers 24(6): 546-555 (2007) |
| 2005 |
| 3 |  | Sylvain Guilley,
Philippe Hoogvorst,
Yves Mathieu,
Renaud Pacalet:
The "Backend Duplication" Method.
CHES 2005: 383-397 |
| 2004 |
| 2 |  | Sylvain Guilley,
Philippe Hoogvorst,
Yves Mathieu,
Renaud Pacalet,
Jean Provost:
CMOS Structures Suitable for Secured Hardware.
DATE 2004: 1414-1415 |
| 2003 |
| 1 |  | Christophe Cunat,
Jean Gobert,
Yves Mathieu:
A coprocessor for real-time MPEG4 facial animation on mobiles.
ESTImedia 2003: 102-108 |