 | 2012 |
| 16 |  | Steven Hsu,
Amit Agarwal,
Mark Anders,
Sanu Mathew,
Himanshu Kaul,
Farhana Sheikh,
Ram Krishnamurthy:
A 280mV-to-1.1V 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22nm CMOS.
ISSCC 2012: 178-180 |
| 15 |  | Himanshu Kaul,
Mark Anders,
Sanu Mathew,
Steven Hsu,
Amit Agarwal,
Farhana Sheikh,
Ram Krishnamurthy,
Shekhar Borkar:
A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS.
ISSCC 2012: 182-184 |
| 14 |  | Farhana Sheikh,
Sanu Mathew,
Mark Anders,
Himanshu Kaul,
Steven Hsu,
Amit Agarwal,
Ram Krishnamurthy,
Shekhar Borkar:
A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex and pixel shading in 32nm CMOS.
ISSCC 2012: 184-186 |
| 2011 |
| 13 |  | Ram Krishnamurthy,
Sanu Mathew,
Farhana Sheikh:
High-performance energy-efficient encryption in the sub-45nm CMOS Era.
DAC 2011: 332 |
| 12 |  | Amit Agarwal,
Steven Hsu,
Sanu Mathew,
Mark Anders,
Himanshu Kaul,
Farhana Sheikh,
Ram Krishnamurthy:
A 128×128b high-speed wide-and match-line content addressable memory in 32nm CMOS.
ESSCIRC 2011: 83-86 |
| 11 |  | Sanu Mathew,
Farhana Sheikh,
Michael E. Kounavis,
Shay Gueron,
Amit Agarwal,
Steven Hsu,
Himanshu Kaul,
Mark Anders,
Ram Krishnamurthy:
53 Gbps Native GF(2 4) 2 Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors.
J. Solid-State Circuits 46(4): 767-776 (2011) |
| 2010 |
| 10 |  | Mark Anders,
Himanshu Kaul,
Steven Hsu,
Amit Agarwal,
Sanu Mathew,
Farhana Sheikh,
Ram Krishnamurthy,
Shekhar Borkar:
A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8×8 mesh network-on-chip in 45nm CMOS.
ISSCC 2010: 110-111 |
| 9 |  | Amit Agarwal,
Sanu Mathew,
Steven Hsu,
Mark Anders,
Himanshu Kaul,
Farhana Sheikh,
Rajaraman Ramanarayanan,
Suresh Srinivasan,
Ram Krishnamurthy,
Shekhar Borkar:
A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS.
ISSCC 2010: 328-329 |
| 8 |  | Himanshu Kaul,
Mark Anders,
Sanu Mathew,
Steven Hsu,
Amit Agarwal,
Ram Krishnamurthy,
Shekhar Borkar:
A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS.
J. Solid-State Circuits 45(1): 95-102 (2010) |
| 2009 |
| 7 |  | Himanshu Kaul,
Mark Anders,
Sanu Mathew,
Steven Hsu,
Amit Agarwal,
Ram Krishnamurthy,
Shekhar Borkar:
A 300mV 494GOPS/W reconfigurable dual-supply 4-Way SIMD vector processing accelerator in 45nm CMOS.
ISSCC 2009: 260-261 |
| 6 |  | Suresh Srinivasan,
Sanu Mathew,
Vasantha Erraguntla,
Ram Krishnamurthy:
A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS.
VLSI Design 2009: 301-306 |
| 2008 |
| 5 |  | Rajaraman Ramanarayanan,
Sanu Mathew,
Vasantha Erraguntla,
Ram Krishnamurthy,
Shay Gueron:
A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores.
VLSI Design 2008: 273-278 |
| 2007 |
| 4 |  | Sanu Mathew,
David Harris,
Mark Anders,
Steven Hsu,
Ram Krishnamurthy:
A 2.4GHz 256/1024-bit Encryption Accelerator reconfigurable Montgomery multiplier in 90nm CMOS.
SoCC 2007: 25-28 |
| 2005 |
| 3 |  | David Harris,
Ram Krishnamurthy,
Mark Anders,
Sanu Mathew,
Steven Hsu:
An Improved Unified Scalable Radix-2 Montgomery Multiplier.
IEEE Symposium on Computer Arithmetic 2005: 172-178 |
| 2 |  | Vojin G. Oklobdzija,
Bart R. Zeydel,
Hoang Q. Dao,
Sanu Mathew,
Ram Krishnamurthy:
Comparison of high-performance VLSI adders in the energy-delay space.
IEEE Trans. VLSI Syst. 13(6): 754-758 (2005) |
| 2003 |
| 1 |  | Vojin G. Oklobdzija,
Bart R. Zeydel,
Hoang Q. Dao,
Sanu Mathew,
Ram Krishnamurthy:
Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders.
IEEE Symposium on Computer Arithmetic 2003: 272-279 |