 | 2011 |
| 49 |  | Noboru Ishihara,
Shuhei Amakawa,
Kazuya Masu:
RF CMOS Integrated Circuit: History, Current Status and Future Prospects.
IEICE Transactions 94-A(2): 556-567 (2011) |
| 48 |  | Yusaku Ito,
Kenichi Okada,
Kazuya Masu:
A Tunable Wideband Frequency Synthesizer Using LC-VCO and Mixer for Reconfigurable Radio Transceivers.
J. Electrical and Computer Engineering 2011: (2011) |
| 2010 |
| 47 |  | Takashi Sato,
Takumi Uezono,
Noriaki Nakayama,
Kazuya Masu:
Decomposition of drain-current variation into gain-factor and threshold voltage variations.
ISCAS 2010: 1053-1056 |
| 46 |  | Takumi Uezono,
Tomoyuki Takahashi,
Michihiro Shintani,
Kazumi Hatayama,
Kazuya Masu,
Hiroyuki Ochi,
Takashi Sato:
Scan based process parameter estimation through path-delay inequalities.
ISCAS 2010: 3553-3556 |
| 45 |  | Takanori Date,
Shiho Hagiwara,
Kazuya Masu,
Takashi Sato:
Robust importance sampling for efficient SRAM yield analysis.
ISQED 2010: 15-21 |
| 44 |  | Shiho Hagiwara,
Koh Yamanaga,
Ryo Takahashi,
Kazuya Masu,
Takashi Sato:
Linear time calculation of state-dependent power distribution network capacitance.
ISQED 2010: 75-80 |
| 43 |  | Koh Yamanaga,
Kazuya Masu,
Takashi Sato:
Application of generalized scattering matrix for prediction of power supply noise.
SLIP 2010: 83-90 |
| 42 |  | Takumi Uezono,
Tomoyuki Takahashi,
Michihiro Shintani,
Kazumi Hatayama,
Kazuya Masu,
Hiroyuki Ochi,
Takashi Sato:
Path clustering for adaptive test.
VTS 2010: 15-20 |
| 41 |  | Shiho Hagiwara,
Koh Yamanaga,
Ryo Takahashi,
Kazuya Masu,
Takashi Sato:
Linear Time Calculation of On-Chip Power Distribution Network Capacitance Considering State-Dependence.
IEICE Transactions 93-A(12): 2409-2416 (2010) |
| 40 |  | Takumi Uezono,
Kazuya Masu,
Takashi Sato:
A Time-Slicing Ring Oscillator for Capturing Time-Dependent Delay Degradation and Power Supply Voltage Fluctuation.
IEICE Transactions 93-C(3): 324-331 (2010) |
| 39 |  | Koh Yamanaga,
Shuhei Amakawa,
Kazuya Masu,
Takashi Sato:
A Universal Equivalent Circuit Model for Ceramic Capacitors.
IEICE Transactions 93-C(3): 347-354 (2010) |
| 2009 |
| 38 |  | Michihiro Shintani,
Takumi Uezono,
Tomoyuki Takahashi,
Hiroyuki Ueyama,
Takashi Sato,
Kazumi Hatayama,
Takashi Aikyo,
Kazuya Masu:
An Adaptive Test for Parametric Faults Based on Statistical Timing Information.
Asian Test Symposium 2009: 151-156 |
| 37 |  | Takeshi Ito,
Kenichi Okada,
Kazuya Masu:
Characterization of On-Chip Multiport Inductors for Small-Area RF Circuits.
IEEE Trans. on Circuits and Systems 56-I(8): 1590-1597 (2009) |
| 36 |  | Hirotaka Sugawara,
Kenichi Okada,
Kazuya Masu:
Tunable CMOS LNA Using a Variable Inductor for a Reconfigurable RF Circuit.
IEICE Transactions 92-A(2): 401-410 (2009) |
| 35 |  | Takumi Uezono,
Takashi Sato,
Kazuya Masu:
One-Shot Voltage-Measurement Circuit Utilizing Process Variation.
IEICE Transactions 92-A(4): 1024-1030 (2009) |
| 34 |  | Shiho Hagiwara,
Takashi Sato,
Kazuya Masu:
Analytical Estimation of Path-Delay Variation for Multi-Threshold CMOS Circuits.
IEICE Transactions 92-A(4): 1031-1038 (2009) |
| 33 |  | Koh Yamanaga,
Takashi Sato,
Kazuya Masu:
2-Port Modeling Technique for Surface-Mount Passive Components Using Partial Inductance Concept.
IEICE Transactions 92-A(4): 976-982 (2009) |
| 2008 |
| 32 |  | Susumu Sadoshima,
Satoshi Fukuda,
Tackya Yammouch,
Hiroyuki Ito,
Kenichi Okada,
Kazuya Masu:
Small-area CMOS RF distributed mixer using multi-port inductors.
ASP-DAC 2008: 105-106 |
| 31 |  | Takashi Sato,
Hiroyuki Ueyama,
Noriaki Nakayama,
Kazuya Masu:
Determination of optimal polynomial regression function to decompose on-die systematic and random variations.
ASP-DAC 2008: 518-523 |
| 30 |  | Akiko Mineyama,
Hiroyuki Ito,
Takahiro Ishii,
Kenichi Okada,
Kazuya Masu:
LVDS-type on-chip transmision line interconnect with passive equalizers in 90nm CMOS process.
ASP-DAC 2008: 97-98 |
| 29 |  | Masanori Imai,
Takashi Sato,
Noriaki Nakayama,
Kazuya Masu:
Non-parametric statistical static timing analysis: an SSTA framework for arbitrary distribution.
DAC 2008: 698-701 |
| 28 |  | Tackya Yammouch,
Kenichi Okada,
Kazuya Masu:
Physical Modeling of MEMS Variable Inductor.
IEEE Trans. on Circuits and Systems 55-II(5): 419-422 (2008) |
| 27 |  | Shiho Hagiwara,
Takumi Uezono,
Takashi Sato,
Kazuya Masu:
Application of Correlation-Based Regression Analysis for Improvement of Power Distribution Network.
IEICE Transactions 91-A(4): 951-956 (2008) |
| 26 |  | Masanori Imai,
Takashi Sato,
Noriaki Nakayama,
Kazuya Masu:
An Evaluation Method of the Number of Monte Carlo STA Trials for Statistical Path Delay Analysis.
IEICE Transactions 91-A(4): 957-964 (2008) |
| 25 |  | Kazuya Masu,
Kenichi Okada:
Reconfigurable RF CMOS Circuit for Cognitive Radio.
IEICE Transactions 91-B(1): 10-13 (2008) |
| 24 |  | Kenta Yamada,
Takashi Sato,
Shuhei Amakawa,
Noriaki Nakayama,
Kazuya Masu,
Shigetaka Kumashiro:
Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress.
IEICE Transactions 91-C(7): 1142-1150 (2008) |
| 2007 |
| 23 |  | Shiho Hagiwara,
Takumi Uezono,
Takashi Sato,
Kazuya Masu:
Improvement of power distribution network using correlation-based regression analysis.
ACM Great Lakes Symposium on VLSI 2007: 513-516 |
| 22 |  | Satoshi Fukuda,
D. Kawazoe,
Kenichi Okada,
Kazuya Masu:
Reconfigurable CMOS Low Noise Amplifier Using Variable Bias Circuit for Self Compensation.
ASP-DAC 2007: 104-105 |
| 21 |  | Junki Seita,
Hiroyuki Ito,
Kenichi Okada,
Takashi Sato,
Kazuya Masu:
A Multi-Drop Transmission-Line Interconnect in Si LSI.
ASP-DAC 2007: 118-119 |
| 20 |  | K. Ohashi,
Yusaku Ito,
Yoshiaki Yoshihara,
Kenichi Okada,
Kazuya Masu:
A Wideband CMOS LC-VCO Using Variable Inductor.
ASP-DAC 2007: 98-99 |
| 19 |  | Takashi Sato,
Takumi Uezono,
Shiho Hagiwara,
Kenichi Okada,
Shuhei Amakawa,
Noriaki Nakayama,
Kazuya Masu:
A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation.
ISQED 2007: 21-26 |
| 18 |  | Takashi Sato,
Shiho Hagiwara,
Takumi Uezono,
Kazuya Masu:
Weakness Identification for Effective Repair of Power Distribution Network.
PATMOS 2007: 222-231 |
| 17 |  | Shuhei Amakawa,
Takumi Uezono,
Takashi Sato,
Kenichi Okada,
Kazuya Masu:
Adaptable wire-length distribution with tunable occupation probability.
SLIP 2007: 1-8 |
| 16 |  | Hiroyuki Ito,
Hideyuki Sugita,
Kenichi Okada,
Tatsuya Ito,
Kazuhisa Itoi,
Masakazu Sato,
Ryozo Yamauchi,
Kazuya Masu:
Low-Loss Distributed Constant Passive Devices Using Wafer-Level Chip Scale Package Technology.
IEICE Transactions 90-C(3): 641-643 (2007) |
| 2006 |
| 15 |  | D. Kawazoe,
Hirotaka Sugawara,
Tatsuya Ito,
Kenichi Okada,
Kazuya Masu:
Reconfigurable CMOS low noise amplifier for self compensation.
ISCAS 2006 |
| 14 |  | Takumi Uezono,
Kenichi Okada,
Kazuya Masu:
Via Distribution Model for Yield Estimation.
ISQED 2006: 479-484 |
| 13 |  | Kenichi Okada,
Takumi Uezono,
Kazuya Masu:
Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology.
PATMOS 2006: 181-190 |
| 12 |  | Takumi Uezono,
Kenichi Okada,
Kazuya Masu:
Statistical Modeling of a Via Distribution for Yield Estimation.
IEICE Transactions 89-A(12): 3579-3584 (2006) |
| 11 |  | Kazuya Masu,
Kenichi Okada,
Hiroyuki Ito:
RF Passive Components Using Metal Line on Si CMOS.
IEICE Transactions 89-C(6): 681-691 (2006) |
| 2005 |
| 10 |  | Junpei Inoue,
Hiroyuki Ito,
Shinichiro Gomi,
Takanori Kyogoku,
Takumi Uezono,
Kenichi Okada,
Kazuya Masu:
Evaluation of on-chip transmission line interconnect using wire length distribution.
ASP-DAC 2005: 133-138 |
| 9 |  | Kenichi Okada,
Yoshiaki Yoshihara,
Hirotaka Sugawara,
Kazuya Masu:
A dynamic reconfigurable RF circuit architecture.
ASP-DAC 2005: 683-686 |
| 8 |  | Takanori Kyogoku,
Junpei Inoue,
Hidenari Nakashima,
Takumi Uezono,
Kenichi Okada,
Kazuya Masu:
Wire Length Distribution Model Considering Core Utilization for System on Chip.
ISVLSI 2005: 276-277 |
| 7 |  | Takumi Uezono,
Junpei Inoue,
Takanori Kyogoku,
Kenichi Okada,
Kazuya Masu:
Prediction of delay time for future LSI using on-chip transmission line interconnects.
SLIP 2005: 7-12 |
| 6 |  | Hidenari Nakashima,
Junpei Inoue,
Kenichi Okada,
Kazuya Masu:
Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model.
IEICE Transactions 88-A(12): 3358-3366 (2005) |
| 5 |  | Hidenari Nakashima,
Naohiro Takagi,
Junpei Inoue,
Kenichi Okada,
Kazuya Masu:
Evaluation of X Architecture Using Interconnect Length Distribution.
IEICE Transactions 88-A(12): 3437-3444 (2005) |
| 4 |  | Takanori Kyogoku,
Junpei Inoue,
Hidenari Nakashima,
Takumi Uezono,
Kenichi Okada,
Kazuya Masu:
Wire Length Distribution Model for System LSI.
IEICE Transactions 88-A(12): 3445-3452 (2005) |
| 3 |  | Yoshiaki Yoshihara,
Hirotaka Sugawara,
Hiroyuki Ito,
Kenichi Okada,
Kazuya Masu:
Wide Tuning Range LC-VCO Using Variable Inductor for Reconfigurable RF Circuit.
IEICE Transactions 88-A(2): 507-512 (2005) |
| 2004 |
| 2 |  | Hidenari Nakashima,
Junpei Inoue,
Kenichi Okada,
Kazuya Masu:
ULSI Interconnect Length Distribution Model Considering Core Utilization.
DATE 2004: 1210-1217 |
| 1 |  | Yoshiaki Yoshihara,
Hirotaka Sugawara,
Hiroyuki Ito,
Kenichi Okada,
Kazuya Masu:
Inductance-Tuned LC-VCO for Reconfigurable RF Circuit Design.
IEICE Electronic Express 1(7): 156-159 (2004) |