Zied Marrakchi

	2011
19		Umer Farooq, Husain Parvez, Zied Marrakchi, Habib Mehrez: Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGA. ARC 2011: 218-229
18		Emna Amouri, Zied Marrakchi, Habib Mehrez: Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA. ReCoSoC 2011: 1-4
17		Umer Farooq, Husain Parvez, Habib Mehrez, Zied Marrakchi: Exploration of Heterogeneous FPGA Architectures. Int. J. Reconfig. Comp. 2011: (2011)
16		Husain Parvez, Zied Marrakchi, Alp Kilic, Habib Mehrez: Application-Specific FPGA using heterogeneous logic blocks. TRETS 4(3): 24 (2011)
	2010
15		Husain Parvez, Zied Marrakchi, Habib Mehrez: Application Specific FPGA Using Heterogeneous Logic Blocks. ARC 2010: 92-109
14		Husain Parvez, Zied Marrakchi, Habib Mehrez: Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only). FPGA 2010: 290
	2009
13		Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez: Placement and routing techniques to improve delay balance of WDDL netlist in MFPGA. ICECS 2009: 791-794
12		Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez: Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing. ReConFig 2009: 201-206
11		Zied Marrakchi, Hayder Mrabet, Umer Farooq, Habib Mehrez: FPGA Interconnect Topologies Exploration. Int. J. Reconfig. Comp. 2009: (2009)
	2008
10		Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib Mehrez: Efficient tree topology for FPGA interconnect network. ACM Great Lakes Symposium on VLSI 2008: 321-326
9		Umer Farooq, Zied Marrakchi, Hayder Mrabet, Habib Mehrez: The Effect of LUT and Cluster Size on a Tree Based FPGA Architecture. ReConFig 2008: 115-120
8		Husain Parvez, Zied Marrakchi, Habib Mehrez: Enhanced Methodology and Tools for Exploring Domain-Specific Coarse-Grained FPGAs. ReConFig 2008: 121-126
	2007
7		Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez: Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances. NOCS 2007: 243-252
	2006
6		Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez: A multilevel hierarchical interconnection structure for FPGA. FPGA 2006: 225
5		Zied Marrakchi, Hayder Mrabet, Habib Mehrez: Configuration tools for a new multilevel hierarchical FPGA. FPGA 2006: 229
4		Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez: Performances improvement of FPGA using novel multilevel hierarchical interconnection structure. ICCAD 2006: 675-679
3		Zied Marrakchi, Hayder Mrabet, Habib Mehrez: A new Multilevel Hierarchical MFPGA and its suitable configuration tools. ISVLSI 2006: 263-268
2		Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez, André Tissot: Performance Improvement of FPGA Using Novel Multilevel Hierarchical Interconnection Structure. ReCoSoC 2006: 117-123
	2005
1		Hayder Mrabet, Zied Marrakchi, Habib Mehrez, André Tissot: Implementation of Scalable Embedded FPGA for SOC. ReCoSoC 2005: 59-62

Coauthor Index

1	Emna Amouri	[10] [12] [13] [18]
2	Umer Farooq	[9] [11] [17] [19]
3	Alp Kilic	[16]
4	Christian Masson	[7]
5	Habib Mehrez	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
6	Hayder Mrabet	[1] [2] [3] [4] [5] [6] [7] [9] [10] [11] [12] [13]
7	Husain Parvez	[8] [14] [15] [16] [17] [19]
8	Pierre Souillot	[2] [4] [6]
9	André Tissot	[1] [2]

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