Mohammad M. Mansour

	2011
19		Hady Zeineddine, Mohammad M. Mansour: Reconfigurable decoder architectures for Raptor codes. ICASSP 2011: 1669-1672
18		Mohammad M. Mansour, Liang-Gee Chen, Wonyong Sung: Trends in Design and Implementation of Signal Processing Systems [In the Spotlight]. IEEE Signal Process. Mag. 28(6): 192-193 (2011)
17		Hady Zeineddine, Mohammad M. Mansour, R. Puri: Construction and Hardware-Efficient Decoding of Raptor Codes. IEEE Transactions on Signal Processing 59(6): 2943-2960 (2011)
	2009
16		Mohammad M. Mansour: Optimized Architecture for Computing Zadoff-Chu Sequences with Application to LTE. GLOBECOM 2009: 1-6
15		Mohammad M. Mansour: A parallel architecture for 3GPP2/UMB turbo interleavers. ICASSP 2009: 601-604
14		Mohammad M. Mansour: A Parallel Pruned Bit-Reversal Interleaver. IEEE Trans. VLSI Syst. 17(8): 1147-1151 (2009)
13		Mohammad M. Mansour: Parallel lookahead algorithms for pruned interleavers. IEEE Transactions on Communications 57(11): 3188-3194 (2009)
	2008
12		Mohammad M. Mansour: Parallel channel interleavers for 3GPP2/UMB. SiPS 2008: 55-60
	2005
11		Mohammad M. Mansour, Naresh R. Shanbhag: A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes. VLSI Signal Processing 40(3): 371-382 (2005)
	2004
10		Makram M. Mansour, Mohammad M. Mansour, Amit Mehrotra: Analysis of MOS cross-coupled LC-tank oscillators using short-channel device equations. ASP-DAC 2004: 181-185
	2003
9		Mohammad M. Mansour, Naresh R. Shanbhag: Architecture-aware low-density parity-check codes. ISCAS (2) 2003: 57-60
8		Mohammad M. Mansour, Amit Mehrotra: Efficient core designs based on parameterized macrocells with accurate delay models. ISCAS (5) 2003: 517-520
7		Makram M. Mansour, Mohammad M. Mansour, Amit Mehrotra: Parameterized Macrocells with Accurate Delay Models for Core-Based Designs. ISQED 2003: 319-
6		Makram M. Mansour, Mohammad M. Mansour, Amit Mehrotra: Modified Sakurai-Newton Current Model and its Applications to CMOS Digital Circuit Design. ISVLSI 2003: 62-69
5		Mohammad M. Mansour, Naresh R. Shanbhag: VLSI architectures for SISO-APP decoders. IEEE Trans. VLSI Syst. 11(4): 627-650 (2003)
4		Mohammad M. Mansour, Naresh R. Shanbhag: High-throughput LDPC decoders. IEEE Trans. VLSI Syst. 11(6): 976-996 (2003)
	2002
3		Mohammad M. Mansour, Naresh R. Shanbhag: Design methodology for high-speed iterative decoder architectures. ICASSP 2002: 3085-3088
2		Mohammad M. Mansour, Naresh R. Shanbhag: Simplified current and delay models for deep submicron CMOS digital circuits. ISCAS (5) 2002: 109-112
1		Mohammad M. Mansour, Naresh R. Shanbhag: Low-power VLSI decoder architectures for LDPC codes. ISLPED 2002: 284-289

Coauthor Index

1	Liang-Gee Chen	[18]
2	Makram M. Mansour	[6] [7] [10]
3	Amit Mehrotra	[6] [7] [8] [10]
4	R. Puri	[17]
5	Naresh R. Shanbhag	[1] [2] [3] [4] [5] [9] [11]
6	Wonyong Sung	[18]
7	Hady Zeineddine	[17] [19]

Colors in the list of coauthors

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