Salvador Manich

	2010
11		S. Fransi, G. L. Farre, L. Garcia-Deiros, Salvador Manich: Design and implementation of Automatic Test Equipment IP module. European Test Symposium 2010: 244
	2007
10		Salvador Manich, L. Garcia-Deiros, Joan Figueras: Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2046-2058 (2007)
	2004
9		Salvador Manich, L. García, L. Balado, Emili Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras: BIST Technique by Equally Spaced Test Vector Sequences. VTS 2004: 206-216
8		Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, L. Balado, Joan Figueras: On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level. J. Electronic Testing 20(4): 345-355 (2004)
	2003
7		Josep Rius, Alejandro Peidro, Salvador Manich, Rosa Rodriguez-Sánchez: Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental Results. PATMOS 2003: 80-89
	2002
6		Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Rosa Rodríguez-Montañés, Joan Figueras: RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST. ITC 2002: 814-823
	2000
5		Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Paulo J. Teixeira, Marcelino B. Santos: Low Power BIST by Filtering Non-Detecting Vectors. J. Electronic Testing 16(3): 193-202 (2000)
	1999
4		Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, Paulo J. Teixeira, Marcelino B. Santos: Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. ISCAS (1) 1999: 110-113
	1997
3		Salvador Manich, Joan Figueras: Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay model. ED&TC 1997: 597-602
2		Michael Nicolaidis, Ricardo de Oliveira Duarte, Salvador Manich, Joan Figueras: Fault-Secure Parity Prediction Arithmetic Operators. IEEE Design & Test of Computers 14(2): 60-71 (1997)
	1996
1		Salvador Manich, Michael Nicolaidis, Joan Figueras: Enhancing realistic fault secureness in parity prediction array arithmetic operators by I/sub DDQ/ monitoring. VTS 1996: 124-129

Coauthor Index

1	L. Balado (Luz Balado)	[8] [9]
2	Ricardo de Oliveira Duarte	[2]
3	G. L. Farre	[11]
4	Joan Figueras	[1] [2] [3] [4] [5] [6] [8] [9] [10]
5	S. Fransi	[11]
6	A. Gabarró	[5]
7	L. García	[9]
8	L. Garcia-Deiros	[10] [11]
9	Patrick Girard	[4] [5]
10	Loïs Guiller	[4] [5]
11	Christian Landrault	[4] [5]
12	M. Lopez	[5]
13	Emili Lupon	[9]
14	Michael Nicolaidis	[1] [2]
15	Alejandro Peidro	[7]
16	Serge Pravossoudovitch	[4] [5]
17	Rosa Rodríguez-Montañés	[6] [9]
18	Rosa Rodriguez-Sánchez	[7]
19	Marcelino B. Santos (Marcelino Bicho Dos Santos)	[4] [5] [6] [8]
20	Isabel C. Teixeira (Isabel Maria Cacho Teixeira)	[6] [8]
21	João Paulo Teixeira	[6] [8]
22	Paulo J. Teixeira	[4] [5]
23	Josep Rius Vázquez (Josep Rius)	[7] [9]

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