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Chitta Mandal
List of publications from the DBLP Bibliography Server - FAQ
| 2011 | ||
|---|---|---|
| 35 | Chandan Karfa, Kunal Banerjee, Dipankar Sarkar, Chitta Mandal: Equivalence Checking of Array-Intensive Programs. ISVLSI 2011: 156-161 | |
| 34 | Chandan Karfa, Chitta Mandal, Dipankar Sarkar: Verification of Register Transfer Level Low Power Transformations. ISVLSI 2011: 313-314 | |
| 33 | Ariyam Das, Chittaranjan A. Mandal, Chris Reade, Manish Aasawat: An improved greedy construction of minimum connected dominating sets in wireless networks. WCNC 2011: 790-795 | |
| 32 | Soumya Pandit, Chittaranjan A. Mandal, Amit Patra: A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies. VLSI Design 2011: (2011) | |
| 2010 | ||
| 31 | Gopal Paul, Rohit Reddy, Chittaranjan A. Mandal, Bhargab B. Bhattacharya: A BDD-Based Design of an Area-Power Efficient Asynchronous Adder. ISVLSI 2010: 29-34 | |
| 30 | Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal: Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques. ISVLSI 2010: 428-433 | |
| 29 | Gopal Paul, Santosh Biswas, Chittaranjan A. Mandal, Bhargab B. Bhattacharya: A BDD-based approach to design power-aware on-line detectors for digital circuits. SoCC 2010: 343-346 | |
| 28 | Rajiv Misra, Chittaranjan A. Mandal: Minimum Connected Dominating Set Using a Collaborative Cover Heuristic for Ad Hoc Sensor Networks. IEEE Trans. Parallel Distrib. Syst. 21(3): 292-302 (2010) | |
| 27 | Chandan Karfa, Dipankar Sarkar, Chitta Mandal: Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 29(3): 479-492 (2010) | |
| 26 | Soumya Pandit, Chittaranjan A. Mandal, Amit Patra: An automated high-level topology generation procedure for continuous-time SigmaDelta modulator. Integration 43(3): 289-304 (2010) | |
| 2009 | ||
| 25 | Rajiv Misra, Chittaranjan A. Mandal: Location Updates of Mobile Node in Wireless Sensor Networks. MSN 2009: 311-318 | |
| 24 | Soumya Pandit, Chittaranjan A. Mandal, Amit Patra: Systematic Methodology for High-Level Performance Modeling of Analog Systems. VLSI Design 2009: 361-366 | |
| 23 | Rajiv Misra, Chittaranjan A. Mandal: Rotation of CDS via Connected Domatic Partition in Ad Hoc Sensor Networks. IEEE Trans. Mob. Comput. 8(4): 488-499 (2009) | |
| 22 | Rajiv Misra, Chittaranjan A. Mandal: Efficient clusterhead rotation via domatic partition in self-organizing sensor networks. Wireless Communications and Mobile Computing 9(8): 1040-1058 (2009) | |
| 2008 | ||
| 21 | Chandan Karfa, Dipankar Sarkar, Chitta Mandal, P. Kumar: An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 556-569 (2008) | |
| 20 | Soumya Pandit, Sumit K. Bhattacharya, Chittaranjan A. Mandal, Amit Patra: A Fast Exploration Procedure for Analog High-Level Specification Translation. IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1493-1497 (2008) | |
| 2007 | ||
| 19 | Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal, Chris Reade: Hand-in-hand verification of high-level synthesis. ACM Great Lakes Symposium on VLSI 2007: 429-434 | |
| 18 | Rajiv Misra, Chittaranjan A. Mandal: ClusterHead Rotation via Domatic Partition in Self-Organizing Sensor Networks. COMSWARE 2007 | |
| 17 | Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, Chris Reade: Register Sharing Verification During Data-Path Synthesis. ICCTA 2007: 135-140 | |
| 16 | Vinay Vishwakarma, Chittaranjan A. Mandal, Shamik Sural: Automatic Detection of Human Fall in Video. PReMI 2007: 616-623 | |
| 15 | Amit Kumar Mandal, Chittaranjan A. Mandal, Chris Reade: A System for Automatic Evaluation of C Programs: Features and Interfaces. IJWLTT 2(4): 24-39 (2007) | |
| 2006 | ||
| 14 | Soumya Pandit, Chittaranjan A. Mandal, Amit Patra: A formal approach for high level synthesis of linear analog systems. ACM Great Lakes Symposium on VLSI 2006: 345-348 | |
| 13 | Soumya Pandit, Sougata Kar, Chittaranjan A. Mandal, Amit Patra: High level synthesis of higher order continuous time state variable filters with minimum sensitivity and hardware count. DATE 2006: 1203-1204 | |
| 12 | Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade: A Formal Verification Method of Scheduling in High-level Synthesis. ISQED 2006: 71-78 | |
| 11 | Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade: Verification of Scheduling in High-level Synthesis. ISVLSI 2006: 141-146 | |
| 10 | Amit Kumar Mandal, Chittaranjan A. Mandal, Chris Reade: A System for Automatic Evaluation of Programs for Correctness and Performance. WEBIST (2) 2006: 196-203 | |
| 9 | Chittaranjan A. Mandal, Chris Reade: Animating Algorithms over the Web. WEBIST (2) 2006: 403-407 | |
| 8 | Amit Kumar Mandal, Chittaranjan A. Mandal, Chris Reade: A System for Automatic Evaluation of Programs for Correctness and Performance. WEBIST (Selected Papers) 2006: 367-380 | |
| 2004 | ||
| 7 | Arijit Mondal, P. P. Chakrabarti, Chittaranjan A. Mandal: A New Approach to Timing Analysis Using Event Propagation and Temporal Logic. DATE 2004: 1198-1203 | |
| 2002 | ||
| 6 | Bipin Rajendran, Veerbhan Kheterpal, Abhishek Das, Jayanta Majumder, Chittaranjan A. Mandal, P. P. Chakrabarti: Timing analysis of tree-like RLC circuits. ISCAS (4) 2002: 838-841 | |
| 2000 | ||
| 5 | Chittaranjan A. Mandal, R. M. Zimmer: A Genetic Algorithm for the Synthesis of Structured Data Paths. VLSI Design 2000: 206-211 | |
| 4 | Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose: GABIND: a GA approach to allocation and binding for the high-level synthesis of data paths. IEEE Trans. VLSI Syst. 8(6): 747-750 (2000) | |
| 1999 | ||
| 3 | Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose: A design space exploration scheme for data-path synthesis. IEEE Trans. VLSI Syst. 7(3): 331-338 (1999) | |
| 1997 | ||
| 2 | Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose: Design Space Exploration for Data Path Synthesis. VLSI Design 1997: 166-173 | |
| 1996 | ||
| 1 | Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose: Allocation and Binding in Data Path Synthesis Using a Genetic Algorithm Approach. VLSI Design 1996: 122-125 | |
| 1 | Manish Aasawat | [33] |
| 2 | Kunal Banerjee | [35] |
| 3 | Bhargab B. Bhattacharya | [29] [31] |
| 4 | Sumit K. Bhattacharya | [20] |
| 5 | Santosh Biswas | [29] |
| 6 | P. P. Chakrabarti (Partha Pratim Chakrabarti) | [1] [2] [3] [4] [6] [7] |
| 7 | Abhishek Das | [6] |
| 8 | Ariyam Das | [33] |
| 9 | Sujoy Ghose | [1] [2] [3] [4] |
| 10 | Sougata Kar | [13] |
| 11 | Chandan Karfa | [11] [12] [17] [19] [21] [27] [30] [34] [35] |
| 12 | Veerbhan Kheterpal | [6] |
| 13 | P. Kumar | [21] |
| 14 | Jayanta Majumder | [6] |
| 15 | Amit Kumar Mandal | [8] [10] [15] |
| 16 | Rajiv Misra | [18] [22] [23] [25] [28] |
| 17 | Arijit Mondal | [7] |
| 18 | Soumya Pandit | [13] [14] [20] [24] [26] [32] |
| 19 | Amit Patra | [13] [14] [20] [24] [26] [32] |
| 20 | Gopal Paul | [29] [31] |
| 21 | S. R. Pentakota | [11] [12] |
| 22 | Bipin Rajendran | [6] |
| 23 | Chris Reade | [8] [9] [10] [11] [12] [15] [17] [19] [33] |
| 24 | Rohit Reddy | [31] |
| 25 | Dipankar Sarkar | [11] [12] [17] [19] [21] [27] [30] [34] [35] |
| 26 | Shamik Sural | [16] |
| 27 | Vinay Vishwakarma | [16] |
| 28 | R. M. Zimmer | [5] |
Colors in the list of coauthors
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