Hiroshi Makino

	2011
10		Hiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda: Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution. IEEE Trans. on Circuits and Systems 58-II(4): 230-234 (2011)
	2010
9		Shunji Nakata, Hirotsugu Suzuki, Ryota Honda, Takahito Kusumoto, Shin'ichiro Mutoh, Hiroshi Makino, Masayuki Miyama, Yoshio Matsuda: Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit. ISCAS 2010: 2474-2477
	2008
8		Hiroaki Suzuki, Masanori Kurimoto, Tadao Yamanaka, Hidehiro Takata, Hiroshi Makino, Hirofumi Shinohara: Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology. ISLPED 2008: 15-20
7		Masako Fujii, Koji Nii, Hiroshi Makino, Shigeki Ohbayashi, Motoshige Igarashi, Takeshi Kawamura, Miho Yokota, Nobuhiro Tsuda, Tomoaki Yoshizawa, Toshikazu Tsutsui, Naohiko Takeshita, Naofumi Murata, Tomohiro Tanaka, Takanari Fujiwara, Kyoko Asahina, Masakazu Okada, Kazuo Tomita, Masahiko Takeuchi, Shigehisa Yamamoto, Hiromitsu Sugimoto, Hirofumi Shinohara: A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology. IEICE Transactions 91-C(8): 1338-1347 (2008)
	2005
6		Yasumasa Tsukamoto, Koji Nii, Susumu Imaoka, Yuji Oda, Shigeki Ohbayashi, Tomoaki Yoshizawa, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara: Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability. ICCAD 2005: 398-405
5		Niichi Itoh, Yasumasa Tsukamoto, Takeshi Shibagaki, Koji Nii, Hidehiro Takata, Hiroshi Makino: A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure. ISCAS (1) 2005: 73-76
	1998
4		Koji Nii, Hiroshi Makino, Yoshiki Tujihashi, Chikayoshi Morishima, Yasushi Hayakawa, Hiroyuki Nunogami, Takahiko Arakawa, Hisanori Hamano: A low power SRAM using auto-backgate-controlled MT-CMOS. ISLPED 1998: 293-298
	1997
3		Hiroaki Suzuki, Hiroshi Makino, Koichiro Mashiko, Hisanori Hamano: A Floating Point Divider using Redundant Binary Circuits and an Asynchronous Clock Scheme. ICCD 1997: 685-689
	1993
2		Hiroshi Makino, Yasunobu Nakase, Hirofumi Shinohara: A 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary Architecture. ICCD 1993: 202-205
	1980
1		Hiroshi Makino, Makoto Kizawa: An Automatic Translation System Of Non-Segmented Kana Sentences Into Kanji-Kana Sentences. COLING 1980: 295-302

Coauthor Index

1	Takahiko Arakawa	[4]
2	Kyoko Asahina	[7]
3	Masako Fujii	[7]
4	Takanari Fujiwara	[7]
5	Hisanori Hamano	[3] [4]
6	Yasushi Hayakawa	[4]
7	Ryota Honda	[9]
8	Motoshige Igarashi	[7]
9	Susumu Imaoka	[6]
10	Koichiro Ishibashi	[6]
11	Niichi Itoh	[5]
12	Shuhei Iwade	[10]
13	Takeshi Kawamura	[7]
14	Makoto Kizawa	[1]
15	Masanori Kurimoto	[8]
16	Takahito Kusumoto	[9]
17	Koichiro Mashiko	[3]
18	Yoshio Matsuda	[9] [10]
19	Masayuki Miyama	[9] [10]
20	Chikayoshi Morishima	[4]
21	Naofumi Murata	[7]
22	Shin'ichiro Mutoh	[9] [10]
23	Yasunobu Nakase	[2]
24	Shunji Nakata	[9] [10]
25	Koji Nii	[4] [5] [6] [7]
26	Hiroyuki Nunogami	[4]
27	Yuji Oda	[6]
28	Shigeki Ohbayashi	[6] [7]
29	Masakazu Okada	[7]
30	Takeshi Shibagaki	[5]
31	Hirofumi Shinohara	[2] [6] [7] [8]
32	Hiromitsu Sugimoto	[7]
33	Hiroaki Suzuki	[3] [8]
34	Hirotsugu Suzuki	[9] [10]
35	Hidehiro Takata	[5] [8]
36	Naohiko Takeshita	[7]
37	Masahiko Takeuchi	[7]
38	Tomohiro Tanaka	[7]
39	Kazuo Tomita	[7]
40	Nobuhiro Tsuda	[7]
41	Yasumasa Tsukamoto	[5] [6]
42	Toshikazu Tsutsui	[7]
43	Yoshiki Tujihashi	[4]
44	Shigehisa Yamamoto	[7]
45	Tadao Yamanaka	[8]
46	Miho Yokota	[7]
47	Tsutomu Yoshimura	[10]
48	Tomoaki Yoshizawa	[6] [7]

Colors in the list of coauthors

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