Wai-Kei Mak

	2012
41		Shao-Huan Wang, Yu-Yi Liang, Tien-Yu Kuo, Wai-Kei Mak: ISPD11: Power-Driven Flip-Flop Merging and Relocation. IEEE Trans. on CAD of Integrated Circuits and Systems 31(2): 180-191 (2012)
	2011
40		Fong-Yuan Chang, Sheng-Hsiung Chen, Ren-Song Tsay, Wai-Kei Mak: Cut-demand based routing resource allocation and consolidation for routability enhancement. ASP-DAC 2011: 533-538
39		Seong-I. Lei, Wai-Kei Mak: Simultaneous Constrained Pin Assignment and Escape Routing for FPGA-PCB Codesign. FPL 2011: 435-440
38		Shao-Huan Wang, Yu-Yi Liang, Tien-Yu Kuo, Wai-Kei Mak: Power-driven flip-flop merging and relocation. ISPD 2011: 107-114
37		Gaurav Ajwani, Chris Chu, Wai-Kei Mak: FOARS: FLUTE Based Obstacle-Avoiding Rectilinear Steiner Tree Construction. IEEE Trans. on CAD of Integrated Circuits and Systems 30(2): 194-204 (2011)
36		Jackey Z. Yan, Chris C. N. Chu, Wai-Kei Mak: SafeChoice: A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement. IEEE Trans. on CAD of Integrated Circuits and Systems 30(7): 1020-1033 (2011)
	2010
35		De-Yu Liu, Wai-Kei Mak, Ting-Chi Wang: Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design. ACM Great Lakes Symposium on VLSI 2010: 423-428
34		Jackey Z. Yan, Chris Chu, Wai-Kei Mak: SafeChoice: a novel clustering algorithm for wirelength-driven placement. ISPD 2010: 185-192
33		Gaurav Ajwani, Chris Chu, Wai-Kei Mak: FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree construction. ISPD 2010: 27-34
	2009
32		Cheng-Yu Wang, Wai-Kei Mak: Signal skew aware floorplanning and bumper signal assignment technique for flip-chip. ASP-DAC 2009: 341-346
31		Yu-Chen Lin, Wai-Kei Mak, Chris Chu, Ting-Chi Wang: Pad assignment for die-stacking System-in-Package design. ICCAD 2009: 249-255
30		Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak: How to consider shorts and guarantee yield rate improvement for redundant wire insertion. ICCAD 2009: 33-38
29		Chun-Yu Chuang, Wai-Kei Mak: Accurate closed-form parameterized block-based statistical timing analysis applying skew-normal distribution. ISQED 2009: 68-73
	2008
28		Wei-Chung Chao, Wai-Kei Mak: Low-power gated and buffered clock network construction. ACM Trans. Design Autom. Electr. Syst. 13(1): (2008)
27		George A. Constantinides, Wai-Kei Mak, Theerayod Wiangtong: Guest Editorial: Field Programmable Technology. Signal Processing Systems 51(1): 1-2 (2008)
	2007
26		Wai-Kei Mak, Jr-Wei Chen: Voltage Island Generation under Performance Requirement for SoC Designs. ASP-DAC 2007: 798-803
	2006
25		Chien-Chang Chen, Wai-Kei Mak: A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers. ASP-DAC 2006: 777-782
	2005
24		Wai-Kei Mak: Modern FPGA constrained placement. ASP-DAC 2005: 779-784
	2004
23		Hao Li, Wai-Kei Mak, Srinivas Katkoori: Force-Directed Performance-Driven Placement Algorithm for FPGAs. ISVLSI 2004: 193-198
22		Hao Li, Srinivas Katkoori, Wai-Kei Mak: Power minimization algorithms for LUT-based FPGA technology mapping. ACM Trans. Design Autom. Electr. Syst. 9(1): 33-51 (2004)
21		Wai-Kei Mak: I/O placement for FPGAs with multiple I/O standards. IEEE Trans. on CAD of Integrated Circuits and Systems 23(2): 315-321 (2004)
	2003
20		Eric S. H. Wong, Evangeline F. Y. Young, Wai-Kei Mak: Clustering based acyclic multi-way partitioning. ACM Great Lakes Symposium on VLSI 2003: 203-206
19		Wai-Kei Mak: I/O placement for FPGAs with multiple I/O standards. FPGA 2003: 51-57
18		Wai-Kei Mak, Evangeline F. Y. Young: Temporal logic replication for dynamically reconfigurable FPGA partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 22(7): 952-959 (2003)
	2002
17		Wai-Kei Mak, Evangeline F. Y. Young: Temporal logic replication for dynamically reconfigurable FPGA partitioning. ISPD 2002: 190-195
16		Wai-Kei Mak: Min-cut partitioning with functional replication fortechnology-mapped circuits using minimum area overhead. IEEE Trans. on CAD of Integrated Circuits and Systems 21(4): 491-497 (2002)
	2001
15		Hung-Ming Chen, D. F. Wong, Wai-Kei Mak, Hannah Honghua Yang: Faster and more accurate wiring evaluation in interconnect-centric floorplanning. ACM Great Lakes Symposium on VLSI 2001: 62-67
14		Wai-Kei Mak: Min-cut partitioning with functional replication for technology mapped circuits using minimum area overhead. ISPD 2001: 100-105
	2000
13		Wai-Kei Mak, D. F. Wong: A fast hypergraph min-cut algorithm for circuit partitioning. Integration 30(1): 1-11 (2000)
	1999
12		Wai-Kei Mak, D. F. Wong: A fast hypergraph minimum cut algorithm. ISCAS (6) 1999: 170-173
11		Wai-Kei Mak, David P. Morton, R. Kevin Wood: Monte Carlo bounding techniques for determining solution quality in stochastic programs. Oper. Res. Lett. 24(1-2): 47-56 (1999)
	1998
10		Wai-Kei Mak, D. F. Wong: Performance-Driven Board-Level Routing for FPGA-Based Logic Emulation (Abstract). FPGA 1998: 260
	1997
9		Wai-Kei Mak, D. F. Wong: Channel Segmentation Design for Symmentrical FPGAs. ICCD 1997: 496-501
8		Wai-Kei Mak, D. F. Wong: Board-level multiterminal net routing for FPGA-based logic emulation. ACM Trans. Design Autom. Electr. Syst. 2(2): 151-167 (1997)
7		Wai-Kei Mak, Martin D. F. Wong: Minimum replication min-cut partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 16(10): 1221-1227 (1997)
6		Wai-Kei Mak, Martin D. F. Wong: On optimal board-level routing for FPGA-based logic emulation. IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 282-289 (1997)
	1996
5		Wai-Kei Mak, D. F. Wong: Minimum replication min-cut partitioning. ICCAD 1996: 205-210
	1995
4		Wai-Kei Mak, D. F. Wong: On Optimal Board-Level Routing for FPGA-Based Logic Emulation. DAC 1995: 552-556
3		Wai-Kei Mak, D. F. Wong: Board-level multi-terminal net routing for FPGA-based logic emulation. ICCAD 1995: 339-344
	1993
2		Mee Yee Chan, Francis Y. L. Chin, Chris Chu, Wai-Kei Mak: Dilation-5 Embedding of 3-Dimensional Grids into Hypercubes. SPDP 1993: 285-289
	1990
1		Richard G. Guy, John S. Heidemann, Wai-Kei Mak, Thomas W. Page Jr., Gerald J. Popek, Dieter Rothmeier: Implementation of the Ficus Replicated File System. USENIX Summer 1990: 63-72

Coauthor Index

1	Gaurav Ajwani	[33] [37]
2	Mee Yee Chan	[2]
3	Fong-Yuan Chang	[30] [40]
4	Wei-Chung Chao	[28]
5	Chien-Chang Chen	[25]
6	Hung-Ming Chen	[15]
7	Jr-Wei Chen	[26]
8	Sheng-Hsiung Chen	[40]
9	Francis Y. L. Chin (Francis Yuk-Lun Chin)	[2]
10	Chris C. N. Chu (Chris Chu, Chris Chong-Nuen Chu)	[2] [31] [33] [34] [36] [37]
11	Chun-Yu Chuang	[29]
12	George A. Constantinides	[27]
13	Richard G. Guy	[1]
14	John S. Heidemann	[1]
15	Srinivas Katkoori	[22] [23]
16	Tien-Yu Kuo	[38] [41]
17	Seong-I. Lei	[39]
18	Hao Li	[22] [23]
19	Yu-Yi Liang	[38] [41]
20	Yu-Chen Lin	[31]
21	De-Yu Liu	[35]
22	David P. Morton	[11]
23	Thomas W. Page Jr.	[1]
24	Gerald J. Popek	[1]
25	Dieter Rothmeier	[1]
26	Ren-Song Tsay	[30] [40]
27	Cheng-Yu Wang	[32]
28	Shao-Huan Wang	[38] [41]
29	Ting-Chi Wang	[31] [35]
30	Theerayod Wiangtong	[27]
31	Eric S. H. Wong	[20]
32	Martin D. F. Wong (D. F. Wong)	[3] [4] [5] [6] [7] [8] [9] [10] [12] [13] [15]
33	R. Kevin Wood	[11]
34	Jackey Z. Yan	[34] [36]
35	Hannah Honghua Yang (Honghua Yang)	[15]
36	Evangeline F. Y. Young (F. Y. Young, Fung Yu Young)	[17] [18] [20]

Colors in the list of coauthors

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