Terrence S. T. Mak

	2012
26		Ra'ed Al-Dujaily, Terrence S. T. Mak, Fei Xia, Alex Yakovlev, Maurizio Palesi: Embedded Transitive Closure Network for Runtime Deadlock Detection in Networks-on-Chip. IEEE Trans. Parallel Distrib. Syst. 23(7): 1205-1215 (2012)
25		Terrence S. T. Mak: Truncation error analysis of MTBF computation for multi-latch synchronizers. Microelectronics Journal 43(2): 160-163 (2012)
	2011
24		Yu Zhou, Terrence S. T. Mak, Alex Yakovlev: Run-Time Concurrency Tuning for Peak Power Modulation in Energy Harvesting Systems. ACSD 2011: 67-76
23		Yu Li, Terrence S. T. Mak, Alex Yakovlev: Redressing timing issues for speed-independent circuits in deep submicron age. DATE 2011: 1376-1381
22		Ra'ed Al-Dujaily, Terrence S. T. Mak, Fei Xia, Alexandre Yakovlev, Maurizio Palesi: Run-time deadlock detection in networks-on-chip using coupled transitive closure networks. DATE 2011: 497-502
21		Ra'ed Al-Dujaily, Terrence S. T. Mak, Kuan Zhou, Kai-Pui Lam, Yicong Meng, Alexandre Yakovlev, Chi-Sang Poon: On-chip dynamic programming networks using 3D-TSV integration. ICSAMOS 2011: 318-325
20		Qiang Liu, Terrence S. T. Mak, Junwen Luo, Wayne Luk, Alexandre Yakovlev: Power adaptive computing system design in energy harvesting environment. ICSAMOS 2011: 33-40
19		Nizar Dahir, Terrence S. T. Mak, Alex Yakovlev: Communication centric on-chip power grid models for networks-on-chip. VLSI-SoC 2011: 180-183
18		Kai-Pui Lam, Terrence S. T. Mak, Chi-Sang Poon: Cycle avoidance in 2D/3D bidirectional graphs using shortest-path dynamic programming network. VLSI-SoC 2011: 354-358
17		Kai-Pui Lam, Terrence S. T. Mak, Chi-Sang Poon: Comparative ODE benchmarking of unidirectional and bidirectional DP networks for 3D-IC. VLSI-SoC 2011: 98-101
	2010
16		Bo Yu, Terrence S. T. Mak, Xiangyu Li, Fei Xia, Alexandre Yakovlev, Yihe Sun, Chi-Sang Poon: A Reconfigurable Hebbian Eigenfilter for Neurophysiological Spike Train Analysis. FPL 2010: 556-561
15		Terrence S. T. Mak, Kai-Pui Lam, H. S. Ng, Guy Rachmuth, Chi-Sang Poon: A CMOS Current-Mode Dynamic Programming Circuit. IEEE Trans. on Circuits and Systems 57-I(12): 3112-3123 (2010)
14		Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk: Wave-pipelined intra-chip signaling for on-FPGA communications. Integration 43(2): 188-201 (2010)
	2009
13		Terrence S. T. Mak, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam: A DP-network for optimal dynamic routing in network-on-chip. CODES+ISSS 2009: 119-128
12		Li Wang, Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung: Throughput Maximization for Wave-pipelined Interconnects using Cascaded Buffers and Transistor Sizing. ISCAS 2009: 1293-1296
	2008
11		Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk: High-throughput interconnect wave-pipelining for global communication in FPGAs. FPGA 2008: 258
10		Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk: Implementation of Wave-Pipelined Interconnects in FPGAs. NOCS 2008: 213-214
9		Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk: Interconnection lengths and delays estimation for communication links in FPGAs. SLIP 2008: 1-10
8		Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk: Global interconnections in FPGAs: modeling and performance analysis. SLIP 2008: 51-58
	2007
7		Terrence S. T. Mak, Kai-Pui Lam, H. S. Ng, Guy Rachmuth, Chi-Sang Poon: A Current-Mode Analog Circuit for Reinforcement Learning Problems. ISCAS 2007: 1301-1304
6		Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam: A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing. NOCS 2007: 173-182
	2006
5		Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk: On-FPGA Communication Architectures and Design Factors. FPL 2006: 1-8
	2004
4		Terrence S. T. Mak, Kai-Pui Lam: Embedded Computation of Maximum-Likelihood Phylogeny Inference Using Platform FPGA. CSB 2004: 512-514
3		Terrence S. T. Mak, Kai-Pui Lam: FPGA-Based Computation for Maximum Likelihood Phylogenetic Tree Evaluation. FPL 2004: 1076-1079
2		Terrence S. T. Mak, Kai-Pui Lam: On Computing Maximum Likelihood Phylogeny Using FPGA p. FPL 2004: 1188
	2003
1		Terrence S. T. Mak, Kai-Pui Lam: High Speed GAML-based Phylogenetic Tree Reconstruction Using HW/SW Codesign. CSB 2003: 470-473

Coauthor Index

1	Ra'ed Al-Dujaily	[21] [22] [26]
2	Peter Y. K. Cheung	[5] [6] [8] [9] [10] [11] [12] [13] [14]
3	Crescenzo D'Alessandro	[8] [10]
4	Nizar Dahir	[19]
5	Kai-Pui Lam	[1] [2] [3] [4] [6] [7] [13] [15] [17] [18] [21]
6	Xiangyu Li	[16]
7	Yu Li	[23]
8	Qiang Liu	[20]
9	Wayne Luk	[5] [6] [8] [9] [10] [11] [13] [14] [20]
10	Junwen Luo	[20]
11	Yicong Meng	[21]
12	H. S. Ng	[7] [15]
13	Maurizio Palesi	[22] [26]
14	Chi-Sang Poon	[7] [15] [16] [17] [18] [21]
15	Guy Rachmuth	[7] [15]
16	N. Pete Sedcole	[5] [6] [8] [9] [10] [11] [12] [14]
17	Yihe Sun	[16]
18	Li Wang	[12]
19	Fei Xia	[16] [22] [26]
20	Alexandre Yakovlev (Alex Yakovlev)	[8] [10] [16] [19] [20] [21] [22] [23] [24] [26]
21	Bo Yu	[16]
22	Kuan Zhou	[21]
23	Yu Zhou	[24]

Last update Sun Jun 3 16:06:10 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page