Ananta K. Majhi

	2012
25		Elif Alpaslan, Bram Kruseman, Ananta K. Majhi, Wilmar M. Heuvelman, Jennifer Dworak: NIM-X: A Noise Index Model-Based X-Filling Technique to Overcome the Power Supply Switching Noise Effects on Path Delay Test. IEEE Trans. on CAD of Integrated Circuits and Systems 31(5): 809-813 (2012)
	2010
24		Elif Alpaslan, Jennifer Dworak, Bram Kruseman, Ananta K. Majhi, Wilmar M. Heuvelman, Paul van de Wiel: NIM- a noise index model to estimate delay discrepancies between silicon and simulation. DATE 2010: 1373-1376
23		Lavanya Jagan, Camelia Hora, Bram Kruseman, Stefan Eichenberger, Ananta K. Majhi, V. Kamakoti: Impact of Temperature on Test Quality. VLSI Design 2010: 276-281
	2009
22		Lavanya Jagan, Ratan Deep Singh, V. Kamakoti, Ananta K. Majhi: Efficient Grouping of Fail Chips for Volume Yield Diagnostics. VLSI Design 2009: 97-102
	2008
21		Stefan Eichenberger, Jeroen Geuzebroek, Camelia Hora, Bram Kruseman, Ananta K. Majhi: Towards a World Without Test Escapes: The Use of Volume Diagnosis to Improve Test Quality. ITC 2008: 1-10
	2007
20		Jeroen Geuzebroek, Erik Jan Marinissen, Ananta K. Majhi, Andreas Glowatz, Friedrich Hapke: Embedded multi-detect ATPG and Its Effect on the Detection of Unmodeled Defects. ITC 2007: 1-10
19		Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi: Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages. VTS 2007: 145-150
18		Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman, Maurice Lousberg, Ananta K. Majhi: Diagnosis of Full Open Defects in Interconnecting Lines. VTS 2007: 158-166
17		Bram Kruseman, Ananta K. Majhi, Guido Gronthoud: On Performance Testing with Path Delay Patterns. VTS 2007: 29-34
16		Ananta K. Majhi, Mohamed Azimane, Guido Gronthoud, Maurice Lousberg, Stefan Eichenberger, Fred Bowen: Memory Testing Under Different Stress Conditions: An Industrial Evaluation CoRR abs/0710.4693: (2007)
15		Jing Wang, Duncan M. Hank Walker, Xiang Lu, Ananta K. Majhi, Bram Kruseman, Guido Gronthoud, Luis Elvira Villagra, Paul J. A. M. van de Wiel, Stefan Eichenberger: Modeling Power Supply Noise in Delay Testing. IEEE Design & Test of Computers 24(3): 226-234 (2007)
	2006
14		Jing Wang, D. M. H. Walker, Ananta K. Majhi, Bram Kruseman, Guido Gronthoud, Luis Elvira Villagra, Paul van de Wiel, Stefan Eichenberger: Power Supply Noise in Delay Testing. ITC 2006: 1-10
	2005
13		Ananta K. Majhi, Mohamed Azimane, Guido Gronthoud, Maurice Lousberg, Stefan Eichenberger, Fred Bowen: Memory Testing Under Different Stress Conditions: An Industrial Evaluation. DATE 2005: 438-443
12		Mohamed Azimane, Ananta K. Majhi, Guido Gronthoud, Maurice Lousberg: A New Algorithm for Dynamic Faults Detection in RAMs. VTS 2005: 177-182
	2004
11		Bram Kruseman, Ananta K. Majhi, Guido Gronthoud, Stefan Eichenberger: On Hazard-free Patterns for Fine-delay Fault Testing. ITC 2004: 213-222
10		Bram Kruseman, Ananta K. Majhi, Camelia Hora, Stefan Eichenberger, Johan Meirlevede: Systematic Defects in Deep Sub-Micron Technologies. ITC 2004: 290-299
9		Mohamed Azimane, Ananta K. Majhi: New Test Methodology for Resistive Open Defect Detection in Memory Address Decoders. VTS 2004: 123-128
	2003
8		Ananta K. Majhi, Guido Gronthoud, Camelia Hora, Maurice Lousberg, Pop Valer, Stefan Eichenberger: Improving Diagnostic Resolution of Delay Faults using Path Delay Fault Model. VTS 2003: 345-350
	2000
7		Ananta K. Majhi, V. D. Agrawak, James Jacob, Lalit M. Patnaik: Line coverage of path delay faults. IEEE Trans. VLSI Syst. 8(5): 610-614 (2000)
	1998
6		Ananta K. Majhi, Vishwani D. Agrawal: Mixed-Signal Test. VLSI Design 1998: 285-288
5		Ananta K. Majhi, Vishwani D. Agrawal: Tutorial: Delay Fault Models and Coverage. VLSI Design 1998: 364-369
4		S. Balajee, Ananta K. Majhi: Automated AC (Timing) Characterization for Digital Circuit Testing. VLSI Design 1998: 374-377
	1996
3		Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal: On test coverage of path delay faults. VLSI Design 1996: 418-421
	1995
2		Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal: An efficient automatic test generation system for path delay faults in combinational circuits. VLSI Design 1995: 161-165
1		Ananta K. Majhi, Lalit M. Patnaik, Srilata Raman: A genetic algorithm-based circuit partitioner for MCMs. Microprocessing and Microprogramming 41(1): 83-96 (1995)

Coauthor Index

1	V. D. Agrawak	[7]
2	Vishwani D. Agrawal	[2] [3] [5] [6]
3	Elif Alpaslan	[24] [25]
4	Daniel Arumí	[18] [19]
5	Mohamed Azimane	[9] [12] [13] [16]
6	S. Balajee	[4]
7	Fred Bowen	[13] [16]
8	Jennifer Dworak	[24] [25]
9	Stefan Eichenberger	[8] [10] [11] [13] [14] [15] [16] [18] [19] [21] [23]
10	Joan Figueras	[18] [19]
11	Jeroen Geuzebroek	[20] [21]
12	Andreas Glowatz	[20]
13	Guido Gronthoud	[8] [11] [12] [13] [14] [15] [16] [17]
14	Friedrich Hapke	[20]
15	Wilmar M. Heuvelman	[24] [25]
16	Camelia Hora	[8] [10] [18] [19] [21] [23]
17	James Jacob	[2] [3] [7]
18	Lavanya Jagan	[22] [23]
19	V. Kamakoti	[22] [23]
20	Bram Kruseman	[10] [11] [14] [15] [17] [18] [19] [21] [23] [24] [25]
21	Maurice Lousberg	[8] [12] [13] [16] [18] [19]
22	Xiang Lu	[15]
23	Erik Jan Marinissen	[20]
24	Johan Meirlevede	[10]
25	Lalit M. Patnaik	[1] [2] [3] [7]
26	Srilata Raman	[1]
27	Rosa Rodríguez-Montañés	[18] [19]
28	Ratan Deep Singh	[22]
29	Pop Valer	[8]
30	Luis Elvira Villagra	[14] [15]
31	D. M. H. Walker (Duncan M. Hank Walker)	[14] [15]
32	Jing Wang	[14] [15]
33	Paul van de Wiel (Paul J. A. M. van de Wiel)	[14] [15] [24]

Colors in the list of coauthors

Last update Sun Jun 3 16:06:10 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page