 | 2012 |
| 20 |  | Yu Cai,
Erich F. Haratsch,
Onur Mutlu,
Ken Mai:
Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis.
DATE 2012: 521-526 |
| 19 |  | Eric S. Chung,
Michael Papamichael,
Gabriel Weisz,
James C. Hoe,
Ken Mai:
Prototype and evaluation of the CoRAM memory architecture for FPGA-based computing.
FPGA 2012: 139-142 |
| 2011 |
| 18 |  | Yu Cai,
Erich F. Haratsch,
Mark McCartney,
Ken Mai:
FPGA-Based Solid-State Drive Prototyping Platform.
FCCM 2011: 101-104 |
| 17 |  | Yu Cai,
Erich F. Haratsch,
Mark McCartney,
Mudit Bhargava,
Ken Mai:
FPGA-based nand flash memory error characterization and solid-state drive prototyping platform (abstract only).
FPGA 2011: 284 |
| 16 |  | Eric S. Chung,
James C. Hoe,
Ken Mai:
CoRAM: an in-fabric memory architecture for FPGA-based computing.
FPGA 2011: 97-106 |
| 2010 |
| 15 |  | Jim Plusquellic,
Ken Mai:
HOST 2010, Proceedings of the 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), 13-14 June 2010, Anaheim Convention Center, California, USA
IEEE Computer Society 2010 |
| 14 |  | Satyanand Nalam,
Mudit Bhargava,
Ken Mai,
Benton H. Calhoun:
Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers.
DAC 2010: 138-143 |
| 13 |  | Mudit Bhargava,
Cagla Cakir,
Ken Mai:
Attack Resistant Sense Amplifier based PUFs (SA-PUF) with Deterministic and Controllable Reliability of PUF Responses.
HOST 2010: 106-111 |
| 12 |  | Craig Teegarden,
Mudit Bhargava,
Ken Mai:
Side-channel Attack Resistant ROM-based AES S-Box.
HOST 2010: 124-129 |
| 11 |  | Eric Menendez,
Ken Mai:
A Comparison of Power-analysis-resistant Digital Circuits.
HOST 2010: 64-69 |
| 10 |  | Eric S. Chung,
Peter A. Milder,
James C. Hoe,
Ken Mai:
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
MICRO 2010: 225-236 |
| 2009 |
| 9 |  | Mudit Bhargava,
Mark McCartney,
Alexander Hoefler,
Ken Mai:
Low-overhead, digital offset compensated, SRAM sense amplifiers.
CICC 2009: 705-708 |
| 8 |  | Satyanand Nalam,
Mudit Bhargava,
Kyle Ringgenberg,
Ken Mai,
Benton H. Calhoun:
A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes.
ICCD 2009: 523-528 |
| 7 |  | Eric S. Chung,
Michael Papamichael,
Eriko Nurvitadhi,
James C. Hoe,
Ken Mai,
Babak Falsafi:
ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs.
TRETS 2(2): (2009) |
| 2008 |
| 6 |  | Eric S. Chung,
Eriko Nurvitadhi,
James C. Hoe,
Babak Falsafi,
Ken Mai:
A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs.
FPGA 2008: 77-86 |
| 5 |  | Eric Menendez,
Ken Mai:
A High-Performance, Low-Overhead, Power-Analysis-Resistant, Single-Rail Logic Style.
HOST 2008: 33-36 |
| 2007 |
| 4 |  | Eric S. Chung,
Eriko Nurvitadhi,
James C. Hoe,
Babak Falsafi,
Ken Mai:
PROToFLEX: FPGA-accelerated Hybrid Functional Simulator.
IPDPS 2007: 1-6 |
| 3 |  | Jangwoo Kim,
Nikos Hardavellas,
Ken Mai,
Babak Falsafi,
James C. Hoe:
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding.
MICRO 2007: 197-209 |
| 2000 |
| 2 |  | Ken Mai,
Tim Paaske,
Nuwan Jayasena,
Ron Ho,
William J. Dally,
Mark Horowitz:
Smart Memories: a modular reconfigurable architecture.
ISCA 2000: 161-171 |
| 1999 |
| 1 |  | Ron Ho,
Ken Mai,
Hema Kapadia,
Mark Horowitz:
Interconnect scaling implications for CAD.
ICCAD 1999: 425-429 |