Hideo Maejima

	2011
5		Osamu Nishii, Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima: A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core. IEICE Transactions 94-C(4): 663-669 (2011)
	2010
4		Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, S. Matsui, Osamu Nishii, Atsushi Hasegawa, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Koichi Terada, Tohru Nojiri, Masashi Satoh, Hiroyuki Mizuno, Kunio Uchiyama, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima: A 45nm 37.3GOPS/W heterogeneous multi-core SoC. ISSCC 2010: 100-101
	2009
3		Yoshitaka Arahori, Katsuhiko Gondow, Hideo Maejima: TCBC: Trap Caching Bounds Checking for C. DASC 2009: 49-56
	1989
2		Nobuyasu Kanekawa, Hideo Maejima, Hatsuhiko Kato, Hirokazu Ihara: Dependable onboard computer systems with a new method-stepwise negotiating voting. FTCS 1989: 13-19
	1986
1		Hideo Maejima, Hiroyuki Kida, Tan Watanabe, Shiro Baba, Keiichi Kurakazu: A 16-Bit Microprocessor with Multi-Register Bank Architecture. FJCC 1986: 1014-1018

Coauthor Index

1	Yoshitaka Arahori	[3]
2	Shiro Baba	[1]
3	Katsuhiko Gondow	[3]
4	Atsushi Hasegawa	[4]
5	Hirokazu Ihara	[2]
6	Makoto Ishikawa	[4] [5]
7	Masayuki Ito	[4] [5]
8	Nobuyasu Kanekawa	[2]
9	Hironori Kasahara	[4] [5]
10	Hatsuhiko Kato	[2]
11	Hiroyuki Kida	[1]
12	Keiji Kimura	[4] [5]
13	Yoshikazu Kiyoshige	[4] [5]
14	Keiichi Kurakazu	[1]
15	S. Matsui	[4]
16	Junichi Miyakoshi	[4] [5]
17	Hiroyuki Mizuno	[4]
18	Osamu Nishii	[4] [5]
19	Yusuke Nitta	[4] [5]
20	Tohru Nojiri	[4]
21	Masashi Satoh	[4]
22	Koichi Terada	[4]
23	Kunio Uchiyama	[4]
24	Yasutaka Wada	[4] [5]
25	Tan Watanabe	[1]
26	Tetsuya Yamada	[4] [5]
27	Yoichi Yuyama	[4] [5]

Colors in the list of coauthors

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