 | 2012 |
|---|
| 5 |       | Tao Wang,
Pei-Wen Luo,
Yu-Shih Su,
Liang-Chia Cheng,
Ding-Ming Kwai,
Yiyu Shi:
Capturing the phantom of the power grid - on the runtime adaptive techniques for noise reduction.
ASP-DAC 2012: 640-645 |
| 2011 |
|---|
| 4 | | Chien-Chih Huang,
Jwu-E Chen,
Pei-Wen Luo,
Chin-Long Wey:
Yield-award placement optimization for Switched-Capacitor analog integrated circuits.
SoCC 2011: 170-173 |
| 3 | | Pei-Wen Luo,
Jwu-E Chen,
Chin-Long Wey:
Design Methodology for Yield Enhancement of Switched-Capacitor Analog Integrated Circuits.
IEICE Transactions 94-A(1): 352-361 (2011) |
| 2009 |
|---|
| 2 | | Jwu-E Chen,
Pei-Wen Luo,
Chin-Long Wey:
Yield evaluation of analog placement with arbitrary capacitor ratio.
ISQED 2009: 179-184 |
| 2008 |
|---|
| 1 | | Pei-Wen Luo,
Jwu-E Chen,
Chin-Long Wey,
Liang-Chia Cheng,
Ji-Jan Chen,
Wen Ching Wu:
Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 2097-2101 (2008) |
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