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| 2010 | ||
|---|---|---|
| 3 | Hsin-Fu Luo, Ming-Der Shieh, Yi-Jun Liu, Chien-Ming Wu: Efficient memory management for FFT processors. ISCAS 2010: 3737-3740 | |
| 2006 | ||
| 2 | Lan-Da Van, Hsin-Fu Luo, Nien-Hsiang Chang, Chun-Ming Huang: A cost-effective reconfigurable accelerator for platform-based SOC design. ISCAS 2006 | |
| 2004 | ||
| 1 | Lan-Da Van, Hsin-Fu Luo, Chien-Ming Wu, Wen-Hsiang Hu, Chun-Ming Huang, Wei-Chang Tsai: A high-performance area-aware DSP processor architecture for video codecs. ICME 2004: 1499-1502 | |
| 1 | Nien-Hsiang Chang | [2] |
| 2 | Wen-Hsiang Hu | [1] |
| 3 | Chun-Ming Huang | [1] [2] |
| 4 | Yi-Jun Liu | [3] |
| 5 | Ming-Der Shieh | [3] |
| 6 | Wei-Chang Tsai | [1] |
| 7 | Lan-Da Van | [1] [2] |
| 8 | Chien-Ming Wu | [1] [3] |
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