 | 2012 |
|---|
| 11 |       | Jason Cong,
Bin Liu,
Guojie Luo,
Raghu Prabhakar:
Towards layout-friendly high-level synthesis.
ISPD 2012: 165-172 |
| 2011 |
|---|
| 10 | | Jason Cong,
Guojie Luo,
Yiyu Shi:
Thermal-aware cell and through-silicon-via co-placement for 3D ICs.
DAC 2011: 670-675 |
| 9 | | Jeonghee Shin,
John A. Darringer,
Guojie Luo,
Alan J. Weger,
C. L. Johnson:
Early chip planning cockpit.
DATE 2011: 863-866 |
| 8 | | Jason Cong,
John Lee,
Guojie Luo:
A unified optimization framework for simultaneous gate sizing and placement under density constraints.
ISCAS 2011: 1207-1210 |
| 7 | | Jeonghee Shin,
John A. Darringer,
Guojie Luo,
Merav Aharoni,
Alexey Lvov,
Gi-Joon Nam,
Michael B. Healy:
Floorplanning challenges in early chip planning.
SoCC 2011: 388-393 |
| 2010 |
|---|
| 6 | | Thorlindur Thorolfsson,
Guojie Luo,
Jason Cong,
Paul D. Franzon:
Logic-on-logic 3D integration and placement.
3DIC 2010: 1-4 |
| 5 | | Jason Cong,
Guojie Luo:
An analytical placer for mixed-size 3D placement.
ISPD 2010: 61-66 |
| 2009 |
|---|
| 4 | | Jason Cong,
Guojie Luo:
A multilevel analytical placement for 3D ICs.
ASP-DAC 2009: 361-366 |
| 2008 |
|---|
| 3 | | Jason Cong,
Guojie Luo:
Highly efficient gradient computation for density-constrained analytical placement methods.
ISPD 2008: 39-46 |
| 2 | | Jason Cong,
Guojie Luo,
Eric Radke:
Highly Efficient Gradient Computation for Density-Constrained Analytical Placement.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2133-2144 (2008) |
| 2007 |
|---|
| 1 | | Jason Cong,
Guojie Luo,
Jie Wei,
Yan Zhang:
Thermal-Aware 3D IC Placement Via Transformation.
ASP-DAC 2007: 780-785 |
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