 | 2011 |
|---|
| 8 |       | Alessandro Strano,
Crispín Gómez Requena,
Daniele Ludovici,
Michele Favalli,
María Engracia Gómez,
Davide Bertozzi:
Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture.
DATE 2011: 661-666 |
| 7 | | Alberto Ghiribaldi,
Daniele Ludovici,
Michele Favalli,
Davide Bertozzi:
System-level infrastructure for boot-time testing and configuration of networks-on-chip with programmable routing logic.
VLSI-SoC 2011: 308-313 |
| 2010 |
|---|
| 6 | | Daniele Ludovici,
Alessandro Strano,
Georgi Nedeltchev Gaydadjiev,
Luca Benini,
Davide Bertozzi:
Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs.
DATE 2010: 679-684 |
| 5 | | Alessandro Strano,
Daniele Ludovici,
Davide Bertozzi:
A library of dual-clock FIFOs for cost-effective and flexible MPSoC design.
ICSAMOS 2010: 20-27 |
| 2009 |
|---|
| 4 | | Daniele Ludovici,
Georgi Nedeltchev Gaydadjiev,
Davide Bertozzi,
Luca Benini:
Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip.
ACM Great Lakes Symposium on VLSI 2009: 125-128 |
| 3 | | Francisco Gilabert Villamón,
Daniele Ludovici,
Simone Medardoni,
Davide Bertozzi,
Luca Benini,
Georgi Nedeltchev Gaydadjiev:
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints.
CISIS 2009: 681-687 |
| 2 | | Daniele Ludovici,
Francisco Gilabert Villamón,
Simone Medardoni,
Crispín Gómez Requena,
María Engracia Gómez,
Pedro López,
Georgi Nedeltchev Gaydadjiev,
Davide Bertozzi:
Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints.
DATE 2009: 562-565 |
| 1 | | Daniele Ludovici,
Alessandro Strano,
Davide Bertozzi,
Luca Benini,
Georgi Gaydadjiev:
Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture.
NOCS 2009: 244-249 |
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