Lori E. Lucke

	2000
5		Chaitali Chakrabarti, Lori E. Lucke: VLSI architectures for weighted order statistic (WOS) filters. Signal Processing 80(8): 1419-1433 (2000)
	1998
4		K. Ito, Lori E. Lucke, Keshab K. Parhi: ILP-based cost-optimal DSP synthesis with module selection and data format conversion. IEEE Trans. VLSI Syst. 6(4): 582-594 (1998)
	1994
3		Kazuhito Ito, Lori E. Lucke, Keshab K. Parhi: Module selection and data format conversion for cost-optimal DSP synthesis. ICCAD 1994: 322-329
2		Lori E. Lucke, Keshab K. Parhi: Parallel processing architectures for rank order and stack filters. IEEE Transactions on Signal Processing 42(5): 1178-1189 (1994)
	1993
1		Lori E. Lucke, Keshab K. Parhi: Data-flow transformations for critical path time reduction in high-level DSP synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 12(7): 1063-1068 (1993)

Coauthor Index

1	Chaitali Chakrabarti	[5]
2	K. Ito	[4]
3	Kazuhito Ito	[3]
4	Keshab K. Parhi	[1] [2] [3] [4]

Colors in the list of coauthors

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