 | 2011 |
|---|
| 6 |       | Chao-Hung Lu,
Hung-Ming Chen,
Chien-Nan Jimmy Liu:
Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits.
J. Inf. Sci. Eng. 27(1): 287-302 (2011) |
| 2009 |
|---|
| 5 | | Chao-Hung Lu,
Hung-Ming Chen,
Chien-Nan Jimmy Liu,
Wen-Yu Shih:
Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design.
DATE 2009: 845-850 |
| 2008 |
|---|
| 4 | | Chao-Hung Lu,
Hung-Ming Chen,
Chien-Nan Jimmy Liu:
Effective decap insertion in area-array SoC floorplan design.
ACM Trans. Design Autom. Electr. Syst. 13(4): (2008) |
| 3 | | Chao-Hung Lu,
Hung-Ming Chen,
Chien-Nan Jimmy Liu:
An Effective Decap Insertion Method Considering Power Supply Noise during Floorplanning.
J. Inf. Sci. Eng. 24(1): 115-127 (2008) |
| 2007 |
|---|
| 2 | | Chao-Hung Lu,
Hung-Ming Chen,
Chien-Nan Jimmy Liu:
On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design.
ASP-DAC 2007: 792-797 |
| 1 | | Chi-Yi Yeh,
Hung-Ming Chen,
Li-Da Huang,
Wei-Ting Wei,
Chao-Hung Lu,
Chien-Nan Jimmy Liu:
Using power gating techniques in area-array SoC floorplan design.
SoCC 2007: 233-236 |
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