Shih-Hsien Lo

	2010
5		Wei Wang, Huaxin Lu, Jooyoung Song, Shih-Hsien Lo, Yuan Taur: Compact modeling of quantum effects in symmetric double-gate MOSFETs. Microelectronics Journal 41(10): 688-692 (2010)
	2007
4		Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy: Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices. Microelectronics Journal 38(8-9): 931-941 (2007)
	2006
3		Koushik K. Das, Shih-Hsien Lo, Ching-Te Chuang: High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header. VLSI Design 2006: 758-761
	2005
2		Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy: Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. ISQED 2005: 410-415
	1999
1		Shih-Hsien Lo, Douglas A. Buchanan, Yuan Taur: Modeling and characterization of quantization, polysilicon depletion, and direct tunneling effects in MOSFETs with ultrathin oxides. IBM Journal of Research and Development 43(3): 327-338 (1999)

Coauthor Index

1	Douglas A. Buchanan	[1]
2	Ching-Te Chuang	[2] [3] [4]
3	Koushik K. Das	[3]
4	Rajiv V. Joshi	[2] [4]
5	Jae-Joon Kim	[2] [4]
6	Keunwoo Kim	[2] [4]
7	Huaxin Lu	[5]
8	Saibal Mukhopadhyay	[2] [4]
9	Kaushik Roy	[2] [4]
10	Jooyoung Song	[5]
11	Yuan Taur	[1] [5]
12	Wei Wang	[5]

Colors in the list of coauthors

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