 | 2010 |
|---|
| 5 |       | Chih-Yen Lo,
Yu-Tsao Hsing,
Li-Ming Denq,
Cheng-Wen Wu:
SOC Test Architecture and Method for 3-D ICs.
IEEE Trans. on CAD of Integrated Circuits and Systems 29(10): 1645-1649 (2010) |
| 2009 |
|---|
| 4 | | Chun-Chuan Chi,
Chih-Yen Lo,
Te-Wen Ko,
Cheng-Wen Wu:
Test Integration for SOC Supporting Very Low-Cost Testers.
Asian Test Symposium 2009: 287-292 |
| 2007 |
|---|
| 3 | | Chih-Yen Lo,
Chen-Hsing Wang,
Kuo-Liang Cheng,
Jing-Reng Huang,
Chih-Wea Wang,
Shin-Moe Wang,
Cheng-Wen Wu:
STEAC: A Platform for Automatic SOC Test Integration.
IEEE Trans. VLSI Syst. 15(5): 541-545 (2007) |
| 2006 |
|---|
| 2 | | Chen-Hsing Wang,
Chih-Yen Lo,
Min-Sheng Lee,
Jen-Chieh Yeh,
Chih-Tsun Huang,
Cheng-Wen Wu,
Shi-Yu Huang:
A network security processor design based on an integrated SOC design and test platform.
DAC 2006: 490-495 |
| 2004 |
|---|
| 1 | | Kuo-Liang Cheng,
Jing-Reng Huang,
Chih-Wea Wang,
Chih-Yen Lo,
Li-Ming Denq,
Chih-Tsun Huang,
Shin-Wei Hung,
Jye-Yuan Lee:
An SOC Test Integration Platform and Its Industrial Realization.
ITC 2004: 1213-1222 |
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