Chen Kang Lo

	2011
3		Chen Kang Lo, Li-Chun Chen, Meng-Huan Wu, Ren-Song Tsay: Cycle-count-accurate processor modeling for fast and accurate system-level simulation. DATE 2011: 341-346
	2010
2		Kai-Li Lin, Chen Kang Lo, Ren-Song Tsay: Source-level timing annotation for fast and accurate TLM computation model generation. ASP-DAC 2010: 235-240
	2009
1		Chen Kang Lo, Ren-Song Tsay: Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal model. ASP-DAC 2009: 558-563

Coauthor Index

1	Li-Chun Chen	[3]
2	Kai-Li Lin	[2]
3	Ren-Song Tsay	[1] [2] [3]
4	Meng-Huan Wu	[3]

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