Yifang Liu

	2011
14		Yifang Liu, Jiang Hu: GPU-Based Parallelization for Fast Circuit Optimization. ACM Trans. Design Autom. Electr. Syst. 16(3): 24 (2011)
13		Yifang Liu, Deng-Shan Wang: Symmetry analysis of the option pricing model with dividend yield from financial markets. Appl. Math. Lett. 24(4): 481-486 (2011)
12		Yifang Liu, Rupesh S. Shelar, Jiang Hu: Simultaneous Technology Mapping and Placement for Delay Minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 30(3): 416-426 (2011)
	2010
11		Daniel K. Beece, Jinjun Xiong, Chandu Visweswariah, Vladimir Zolotov, Yifang Liu: Transistor sizing of custom high-performance digital circuits with parametric yield considerations. DAC 2010: 781-786
10		Yifang Liu, Yu Yang, Jiang Hu: Clustering-based simultaneous task and voltage scheduling for NoC systems. ICCAD 2010: 277-283
9		Venkata Rajesh Mekala, Yifang Liu, Xiaoji Ye, Jiang Hu, Peng Li: Accurate clock mesh sizing via sequential quadraticprogramming. ISPD 2010: 135-142
8		Yifang Liu, Xiangyue Zhu, Juxiang He: Factorization technique and new exact solutions for the modified Camassa-Holm and Degasperis-Procesi equations. Applied Mathematics and Computation 217(4): 1658-1665 (2010)
7		Yifang Liu, Jiang Hu: A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 29(2): 223-234 (2010)
	2009
6		Yifang Liu, Jiang Hu: GPU-based parallelization for fast circuit optimization. DAC 2009: 943-946
5		Yifang Liu, Jiang Hu: A new algorithm for simultaneous gate sizing and threshold voltage assignment. ISPD 2009: 27-34
	2008
4		Yifang Liu, Rupesh S. Shelar, Jiang Hu: Delay-optimal simultaneous technology mapping and placement with applications to timing optimization. ICCAD 2008: 101-106
3		Yifang Liu, Jiang Hu, Weiping Shi: Multi-scenario buffer insertion in multi-core processor designs. ISPD 2008: 15-22
2		Jiquan Zhou, Xiangli Liu, Xiaozhong Yang, Yifang Liu: Novel soliton-like and multi-solitary wave solutions of (3 + 1)-dimensional Burgers equation. Applied Mathematics and Computation 204(1): 461-467 (2008)
1		Yifang Liu, Jiang Hu, Weiping Shi: Buffering Interconnect for Multicore Processor Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2183-2196 (2008)

Coauthor Index

1	Daniel K. Beece	[11]
2	Juxiang He	[8]
3	Jiang Hu	[1] [3] [4] [5] [6] [7] [9] [10] [12] [14]
4	Peng Li	[9]
5	Xiangli Liu	[2]
6	Venkata Rajesh Mekala	[9]
7	Rupesh S. Shelar	[4] [12]
8	Weiping Shi	[1] [3]
9	Chandu Visweswariah	[11]
10	Deng-Shan Wang	[13]
11	Jinjun Xiong	[11]
12	Xiaozhong Yang	[2]
13	Yu Yang	[10]
14	Xiaoji Ye	[9]
15	Jiquan Zhou	[2]
16	Xiangyue Zhu	[8]
17	Vladimir Zolotov	[11]

Colors in the list of coauthors

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