Xun Liu

	2012
43		Xun Liu, Lixin Tian, Yuhai Wu: Exact solutions of four generalized Benjamin-Bona-Mahony equations with any order. Applied Mathematics and Computation 218(17): 8602-8613 (2012)
	2011
42		Xun Liu, Changyu Huang, Wei-Liang Qian, Yong-Chang Huang: Studies on Utilizing the Three Famous International Index Systems to Evaluate Scientific Research Level of Higher Learning Institutions. IJSITA 2(2): 67-77 (2011)
41		Jin Fan, Xiaosi Gu, Xun Liu, Kevin G. Guise, Yunsoo Park, Laura Martin, Ashley de Marchena, Cheuk Y. Tang, Michael J. Minzenberg, Patrick R. Hof: Involvement of the anterior cingulate and frontoinsular cortices in rapid processing of salient facial emotional information. NeuroImage 54(3): 2539-2546 (2011)
	2010
40		Taemin Kim, Xun Liu: A global interconnect reduction technique during high level synthesis. ASP-DAC 2010: 695-700
39		Won Ha Choi, Xun Liu: Case Study: GPU-based implementation of sequence pair based floorplanning using CUDA. ISCAS 2010: 917-920
38		Won Ha Choi, Xun Liu: Case study: Runtime reduction of a buffer insertion algorithm using GPU parallel programming. SoCC 2010: 121-126
37		Xun Liu, Lixin Tian, Yuhai Wu: Application of (G'/G)-expansion method to two nonlinear evolution equations. Applied Mathematics and Computation 217(4): 1376-1384 (2010)
36		Taemin Kim, Xun Liu: A Functional Unit and Register Binding Algorithm for Interconnect Reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 29(4): 641-646 (2010)
35		Liang Wang, Xun Liu, Kevin G. Guise, Robert T. Knight, Jamshid Ghajar, Jin Fan: Effective Connectivity of the Fronto-parietal Network during Attentional Control. J. Cognitive Neuroscience 22(3): 543-553 (2010)
	2009
34		Taemin Kim, Xun Liu: Better than optimum?: register reduction using idle pipelined functional units. ACM Great Lakes Symposium on VLSI 2009: 327-332
33		Tongtong Chen, Xun Liu: A Case Study of Design Optimization through Variable Width Selection. ISCAS 2009: 1361-1364
32		Zhengtao Yu, Xun Liu: Implementing Multiphase Resonant Clocking on a Finite-Impulse Response Filter. IEEE Trans. VLSI Syst. 17(11): 1593-1601 (2009)
	2008
31		Lixia Yang, Xun Liu, Changyong Xu: Hindrances to the Development of Tourism E-Commerce in China. ISECS 2008: 588-591
30		Xun Liu, Nicholas A. Steinmetz, Alison B. Farley, Charles D. Smith, Jane E. Joseph: Mid-fusiform Activation during Object Discrimination Reflects the Process of Differentiating Structural Descriptions. J. Cognitive Neuroscience 20(9): 1711-1726 (2008)
	2007
29		Zhengtao Yu, Marios C. Papaefthymiou, Xun Liu: Skew spreading for peak current reduction. ACM Great Lakes Symposium on VLSI 2007: 461-464
28		Zhengtao Yu, Xun Liu: Design of Rotary Clock Based Circuits. DAC 2007: 43-48
27		Taemin Kim, Xun Liu: Compatibility path based binding algorithm for interconnect reduction in high level synthesis. ICCAD 2007: 435-441
26		Xun Liu, Yuantao Peng, Marios C. Papaefthymiou: RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power CoRR abs/0710.4690: (2007)
25		Zhengtao Yu, Xun Liu: Low-Power Rotary Clock Array Design. IEEE Trans. VLSI Syst. 15(1): 5-12 (2007)
	2006
24		Yuantao Peng, Xun Liu: Low-power repeater insertion with both delay and slew rate constraints. DAC 2006: 302-307
23		Lifang Wu, Xianglong Meng, Xun Liu, Shiju Chen: A New Method of Object Segmentation in the Basketball Videos. ICPR (1) 2006: 319-322
22		Yuantao Peng, Xun Liu: An Efficient Low-Power Repeater-Insertion Scheme. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2726-2736 (2006)
21		Xun Liu, Yuantao Peng, Marios C. Papaefthymiou: Practical repeater insertion for low power: what repeater library do we need? IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 917-924 (2006)
20		Xun Liu, Hongbin Wang, Christine R. Corbly, Jiajie Zhang, Jane E. Joseph: The Involvement of the Inferior Parietal Cortex in the Numerical Stroop Effect and the Distance Effect in a Two-digit Number Comparison Task. J. Cognitive Neuroscience 18(9): 1518-1530 (2006)
	2005
19		Yuantao Peng, Xun Liu: A sensitivity analysis of low-power repeater insertion. ACM Great Lakes Symposium on VLSI 2005: 244-247
18		Yuantao Peng, Xun Liu: Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method. DAC 2005: 813-818
17		Xun Liu, Yuantao Peng, Marios C. Papaefthymiou: RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power. DATE 2005: 1330-1335
16		Zhengtao Yu, Xun Liu: Power Analysis of Rotary Clock. ISVLSI 2005: 150-155
15		Yuantao Peng, Xun Liu: RITC: Repeater Insertion with Timing Target Compensation. ISVLSI 2005: 299-300
14		Xun Liu, Yang Gao, Dong Shao, Ruili Wang: Feedback based Dynamic Autonomous Web Service Composition. SKG 2005: 19
13		Xun Liu, Marios C. Papaefthymiou: HyPE: hybrid power estimation for IP-based systems-on-chip. IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 1089-1103 (2005)
12		Lixin Tian, Jiangbo Zhou, Xun Liu, Guangsheng Zhong: Nonwandering operators in Banach space. Int. J. Math. Mathematical Sciences 2005(24): 3895-3908 (2005)
	2004
11		Yuantao Peng, Xun Liu: Power macromodeling of global interconnects considering practical repeater insertion. ACM Great Lakes Symposium on VLSI 2004: 244-247
10		Xun Liu, Yuantao Peng, Marios C. Papaefthymiou: Practical repeater insertion for low power: what repeater library do we need? DAC 2004: 30-35
9		Xun Liu, Marios C. Papaefthymiou: A Markov chain sequence generator for power macromodeling. IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1048-1062 (2004)
	2003
8		Xun Liu, Marios C. Papaefthymiou: Design of a 20-mb/s 256-state Viterbi decoder. IEEE Trans. VLSI Syst. 11(6): 965-975 (2003)
	2002
7		Xun Liu, Marios C. Papaefthymiou: Design of a high-throughput low-power IS95 Viterbi decoder. DAC 2002: 263-268
6		Xun Liu, Marios C. Papaefthymiou: A Markov chain sequence generator for power macromodeling. ICCAD 2002: 404-411
5		Xun Liu, Marios C. Papaefthymiou: Incorporation of input glitches into power macromodeling. ISCAS (4) 2002: 846-849
4		Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman: Retiming and clock scheduling for digital circuit optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 184-203 (2002)
	2001
3		Xun Liu, Marios C. Papaefthymiou: A static power estimation methodolodgy for IP-based design. DATE 2001: 280-289
	1999
2		Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman: Maximizing Performance by Retiming and Clock Skew Scheduling. DAC 1999: 231-236
1		Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman: Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits. DATE 1999: 643-649

Coauthor Index

1	Shiju Chen	[23]
2	Tongtong Chen	[33]
3	Won Ha Choi	[38] [39]
4	Christine R. Corbly	[20]
5	Jin Fan	[35] [41]
6	Alison B. Farley	[30]
7	Eby G. Friedman	[1] [2] [4]
8	Yang Gao	[14]
9	Jamshid Ghajar	[35]
10	Xiaosi Gu	[41]
11	Kevin G. Guise	[35] [41]
12	Patrick R. Hof	[41]
13	Changyu Huang	[42]
14	Yong-Chang Huang	[42]
15	Jane E. Joseph	[20] [30]
16	Taemin Kim	[27] [34] [36] [40]
17	Robert T. Knight	[35]
18	Ashley de Marchena	[41]
19	Laura Martin	[41]
20	Xianglong Meng	[23]
21	Michael J. Minzenberg	[41]
22	Marios C. Papaefthymiou	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [13] [17] [21] [26] [29]
23	Yunsoo Park	[41]
24	Yuantao Peng	[10] [11] [15] [17] [18] [19] [21] [22] [24] [26]
25	Wei-Liang Qian	[42]
26	Dong Shao	[14]
27	Charles D. Smith	[30]
28	Nicholas A. Steinmetz	[30]
29	Cheuk Y. Tang	[41]
30	Lixin Tian	[12] [37] [43]
31	Hongbin Wang	[20]
32	Liang Wang	[35]
33	Ruili Wang	[14]
34	Lifang Wu	[23]
35	Yuhai Wu	[37] [43]
36	Changyong Xu	[31]
37	Lixia Yang	[31]
38	Zhengtao Yu	[16] [25] [28] [29] [32]
39	Jiajie Zhang	[20]
40	Guangsheng Zhong	[12]
41	Jiangbo Zhou	[12]

Colors in the list of coauthors

Last update Sun Jun 3 16:06:10 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page