 | 2012 |
|---|
| 8 |       | Yen-Hung Lin,
Yun-Jian Lo,
Hian-Syun Tong,
Wen-Hao Liu,
Yih-Lang Li:
Topology-aware buffer insertion and GPU-based massively parallel rerouting for ECO timing optimization.
ASP-DAC 2012: 437-442 |
| 7 | | Wen-Hao Liu,
Yih-Lang Li:
Optimizing the antenna area and separators in layer assignment of multi-layer global routing.
ISPD 2012: 137-144 |
| 6 | | Ke-Ren Dai,
Wen-Hao Liu,
Yih-Lang Li:
NCTU-GR: Efficient Simulated Evolution-Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing.
IEEE Trans. VLSI Syst. 20(3): 459-472 (2012) |
| 2011 |
|---|
| 5 | | Wen-Hao Liu,
Yih-Lang Li:
Negotiation-based layer assignment for via count and via overflow minimization.
ASP-DAC 2011: 539-544 |
| 4 | | Wen-Hao Liu,
Yih-Lang Li,
Kai-Yuan Chao:
High-quality global routing for multiple dynamic supply voltage designs.
ICCAD 2011: 263-269 |
| 2010 |
|---|
| 3 | | Wen-Hao Liu,
Yih-Lang Li,
Hui-Chi Chen:
Minimizing clock latency range in robust clock tree synthesis.
ASP-DAC 2010: 389-394 |
| 2 | | Wen-Hao Liu,
Wei-Chun Kao,
Yih-Lang Li,
Kai-Yuan Chao:
Multi-threaded collision-aware global routing with bounded-length maze routing.
DAC 2010: 200-205 |
| 2009 |
|---|
| 1 | | Ke-Ren Dai,
Wen-Hao Liu,
Yih-Lang Li:
Efficient simulated evolution based rerouting and congestion-relaxed layer assignment on 3-D global routing.
ASP-DAC 2009: 570-575 |
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