 | 2011 |
|---|
| 7 |       | Tzu-Chi Huang,
Hong-Yi Huang,
Jen-Chieh Liu,
Kuo-Hsing Cheng,
Ching-Hsing Luo:
All digital phase-locked loop using active inductor oscillator and novel locking algorithm.
ISCAS 2011: 486-489 |
| 6 | | Kuo-Hsing Cheng,
Kai-Wei Hong,
Chi-Hsiang Chen,
Jen-Chieh Liu:
A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit.
IEEE Trans. VLSI Syst. 19(7): 1218-1228 (2011) |
| 5 | | Kuo-Hsing Cheng,
Jen-Chieh Liu,
Chih-Yu Chang,
Shu-Yu Jiang,
Kai-Wei Hong:
Built-in Jitter Measurement Circuit With Calibration Techniques for a 3-GHz Clock Generator.
IEEE Trans. VLSI Syst. 19(8): 1325-1335 (2011) |
| 4 | | Kuo-Hsing Cheng,
Jen-Chieh Liu,
Hong-Yi Huang,
Yu-Liang Li,
Yong-Jhen Jhu:
A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler.
IEEE Trans. on Circuits and Systems 58-II(8): 492-496 (2011) |
| 2010 |
|---|
| 3 | | Kuo-Hsing Cheng,
Chang-Chien Hu,
Jen-Chieh Liu,
Hong-Yi Huang:
A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop.
DDECS 2010: 285-288 |
| 2009 |
|---|
| 2 | | Jen-Chieh Liu,
Hong-Yi Huang,
Wei-Bin Yang,
Kuo-Hsing Cheng:
0.5V 160-MHz 260uW all digital phase-locked loop.
DDECS 2009: 186-193 |
| 2006 |
|---|
| 1 | | Hong-Yi Huang,
Bo-Ruei Wang,
Jen-Chieh Liu:
High-gain and high-bandwidth rail-to-rail operational amplifier with slew rate boost circuit.
ISCAS 2006 |
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