 | 2012 |
|---|
| 8 |       | Hung-Yi Liu,
Michele Petracca,
Luca P. Carloni:
Compositional system-level design exploration with planning of high-level synthesis.
DATE 2012: 641-646 |
| 2011 |
|---|
| 7 | | Hung-Yi Liu,
Ilias Diakonikolas,
Michele Petracca,
Luca P. Carloni:
Supervised design space exploration by compositional approximation of Pareto sets.
DAC 2011: 399-404 |
| 2009 |
|---|
| 6 | | Wan-Ping Lee,
Hung-Yi Liu,
Yao-Wen Chang:
Voltage-Island Partitioning and Floorplanning Under Timing Constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(5): 690-702 (2009) |
| 2008 |
|---|
| 5 | | Chih-Hung Liu,
Hung-Yi Liu,
Chung-Wei Lin,
Szu-Jui Chou,
Yao-Wen Chang,
Sy-Yen Kuo,
Shih-Yi Yuan,
Yu-Wei Chen:
An Efficient Graph-Based Algorithm for ESD Current Path Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1363-1375 (2008) |
| 2007 |
|---|
| 4 | | Hung-Yi Liu,
Wan-Ping Lee,
Yao-Wen Chang:
A Provably Good Approximation Algorithm for Power Optimization Using Multiple Supply Voltages.
DAC 2007: 887-890 |
| 3 | | Wan-Ping Lee,
Hung-Yi Liu,
Yao-Wen Chang:
An ILP algorithm for post-floorplanning voltage-island generation considering power-network planning.
ICCAD 2007: 650-655 |
| 2006 |
|---|
| 2 | | Wan-Ping Lee,
Hung-Yi Liu,
Yao-Wen Chang:
Voltage island aware floorplanning for power and timing optimization.
ICCAD 2006: 389-394 |
| 1 | | Hung-Yi Liu,
Chung-Wei Lin,
Szu-Jui Chou,
Wei-Ting Tu,
Chih-Hung Liu,
Yao-Wen Chang,
Sy-Yen Kuo:
Current path analysis for electrostatic discharge protection.
ICCAD 2006: 510-515 |
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