Chien-Nan Jimmy Liu

	2012
46		Mu-Shun Matt Lee, Wei-Ting Liao, Chien-Nan Jimmy Liu: Levelized High-Level Current Model of Logic Blocks for Dynamic Supply Noise Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 31(6): 845-857 (2012)
	2011
45		Chia-Jen Chang, Pao-Jen Huang, Tai-Chen Chen, Chien-Nan Jimmy Liu: ILP-based inter-die routing for 3D ICs. ASP-DAC 2011: 330-335
44		Chia-Wei Chang, Hong-Zu Chou, Kai-Hui Chang, Jie-Hong Roland Jiang, Chien-Nan Jimmy Liu, Chiu-Han Hsiao, Sy-Yen Kuo: Constraint generation for software-based post-silicon bug masking with scalable resynthesis technique for constraint optimization. ISQED 2011: 174-181
43		Chin-Lung Chuang, Chien-Nan Jimmy Liu: Hybrid Testbench Acceleration for Reducing Communication Overhead. IEEE Design & Test of Computers 28(2): 40-51 (2011)
42		Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu: Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits. J. Inf. Sci. Eng. 27(1): 287-302 (2011)
	2010
41		Chin-Cheng Kuo, Yen-Lung Chen, I-Ching Tsai, Li-Yu Chan, Chien-Nan Jimmy Liu: Behavior-level yield enhancement approach for large-scaled analog circuits. DAC 2010: 903-908
40		Hsiu-Wen Li, Ren-Hong Fu, Hsin-Yu Luo, Chien-Nan Jimmy Liu: Automatic circuit adjustment technique for process sensitivity reduction and yield improvement. ISCAS 2010: 2582-2585
39		Mu-Shun Matt Lee, Kuo-Sheng Lai, Chia-Ling Hsu, Chien-Nan Jimmy Liu: Dynamic IR drop estimation at gate level with standard library information. ISCAS 2010: 2606-2609
38		Chin-Cheng Kuo, Chien-Nan Jimmy Liu: Fast and Accurate Analysis of Supply Noise Effects in PLL With Noise Interactions. IEEE Trans. on Circuits and Systems 57-I(1): 44-52 (2010)
37		Mu-Shun Matt Lee, Chien-Nan Jimmy Liu: Dynamic Supply Current Waveform Estimation with Standard Library Information. IEICE Transactions 93-A(3): 595-606 (2010)
36		Yuhwai Tseng, Chauchin Su, Chien-Nan Jimmy Liu: Measuring the Transmission Characteristic of the Human Body in an Electrostatic-Coupling Intra Body Communication System Using a Square Test Stimulus. IEICE Transactions 93-A(3): 664-668 (2010)
35		Yuhwai Tseng, Chauchin Su, Chien-Nan Jimmy Liu: Measurement and Evaluation of the Bioelectrical Impedance of the Human Body by Deconvolution of a Square Wave. IEICE Transactions 93-D(6): 1656-1660 (2010)
	2009
34		Chin-Cheng Kuo, Pei-Syun Lin, Chien-Nan Jimmy Liu: A SCORE macromodel for PLL designs to analyze supply noise interaction issues at behavioral level. ASP-DAC 2009: 516-521
33		Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu, Wen-Yu Shih: Package routability- and IR-drop-aware finger/pad assignment in chip-package co-design. DATE 2009: 845-850
32		Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou: Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging. IEEE Trans. on CAD of Integrated Circuits and Systems 28(2): 272-284 (2009)
31		Hungwen Lu, Chauchin Su, Chien-Nan Jimmy Liu: A Tree-Topology Multiplexer for Multiphase Clock System. IEEE Trans. on Circuits and Systems 56-I(1): 124-131 (2009)
30		Chin-Cheng Kuo, Meng-Jung Lee, Chien-Nan Jimmy Liu, Ching-Ji Huang: Fast Statistical Analysis of Process Variation Effects Using Accurate PLL Behavioral Models. IEEE Trans. on Circuits and Systems 56-I(6): 1160-1172 (2009)
29		Hungwen Lu, Hsin-Wen Wang, Chauchin Su, Chien-Nan Jimmy Liu: Design of an All-Digital LVDS Driver. IEEE Trans. on Circuits and Systems 56-I(8): 1635-1644 (2009)
28		Yuhwai Tseng, Chauchin Su, Chien-Nan Jimmy Liu: Analysis and Design of Wide-Band Digital Transmission in an Electrostatic-Coupling Intra-Body Communication System. IEICE Transactions 92-B(11): 3557-3563 (2009)
27		Kuo-Hsing Cheng, Yu-Chang Tsai, Chien-Nan Jimmy Liu, Kai-Wei Hong, Chin-Cheng Kuo: A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application. IEICE Transactions 92-C(7): 964-972 (2009)
	2008
26		Mu-Shun Matt Lee, Chin-Hsun Lin, Chien-Nan Jimmy Liu, Shih-Che Lin: Quick supply current waveform estimation at gate level using existed cell library information. ACM Great Lakes Symposium on VLSI 2008: 135-138
25		Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu: Effective decap insertion in area-array SoC floorplan design. ACM Trans. Design Autom. Electr. Syst. 13(4): (2008)
24		Chih-Hu Wang, Bor-Sen Chen, Bore-Kuen Lee, Tsu-Tian Lee, Chien-Nan Jimmy Liu, Chauchin Su: Long-Range Prediction for Real-Time MPEG Video Traffic: An Hinfty Filter Approach. IEEE Trans. Circuits Syst. Video Techn. 18(12): 1771-1775 (2008)
23		Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu: An Effective Decap Insertion Method Considering Power Supply Noise during Floorplanning. J. Inf. Sci. Eng. 24(1): 115-127 (2008)
	2007
22		Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu: On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design. ASP-DAC 2007: 792-797
21		Chi-Yi Yeh, Hung-Ming Chen, Li-Da Huang, Wei-Ting Wei, Chao-Hung Lu, Chien-Nan Jimmy Liu: Using power gating techniques in area-array SoC floorplan design. SoCC 2007: 233-236
20		Chin-Lung Chuang, Wei-Hsiang Cheng, Dong-Jung Lu, Chien-Nan Jimmy Liu: Hybrid Approach to Faster Functional Verification with Full Visibility. IEEE Design & Test of Computers 24(2): 154-162 (2007)
19		Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou: Observability Analysis on HDL Descriptions for Effective Functional Validation. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1509-1521 (2007)
18		Wen-Tsan Hsieh, Chi-Chia Yu, Chien-Nan Jimmy Liu, Yi-Fang Chiu: An Efficient Approach with Scaling Capability to Improve Existing Memory Power Model. IEICE Transactions 90-A(5): 1038-1044 (2007)
17		Chih-Yang Hsu, Wen-Tsan Hsieh, Chien-Nan Jimmy Liu, Jing-Yang Jou: A Tableless Approach for High-Level Power Modeling Using Neural Networks. J. Inf. Sci. Eng. 23(1): 71-90 (2007)
	2006
16		Wei-Hsiang Cheng, Chin-Lung Chuang, Chien-Nan Jimmy Liu: An efficient mechanism to provide full visibility for hardware debugging. ISCAS 2006
15		Wen-Tsan Hsieh, Chi-Chia Yu, Chien-Nan Jimmy Liu, Yi-Fang Chiu: A Scalable Power Modeling Approach for Embedded Memory Using LIB Format. PATMOS 2006: 543-552
14		Chin-Cheng Kuo, Chien-Nan Jimmy Liu: On Efficient Behavioral Modeling to Accurately Predict Supply Noise Effects of PLL Designs in Real Systems. VLSI-SoC 2006: 116-121
13		Chin-Cheng Kuo, Yu-Chien Wang, Chien-Nan Jimmy Liu: An Efficient Approach to Build Accurate Behavioral Models of PLL Designs. IEICE Transactions 89-A(2): 391-398 (2006)
12		Wenliang Tseng, Chien-Nan Jimmy Liu, Chauchin Su: Passive Reduced-Order Macro-Modeling for Linear Time-Delay Interconnect Systems. IEICE Transactions 89-C(11): 1713-1718 (2006)
	2005
11		Chin-Cheng Kuo, Yu-Chien Wang, Chien-Nan Jimmy Liu: An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs. ACM Great Lakes Symposium on VLSI 2005: 286-290
10		Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou: An observability measure to enhance statement coverage metric for proper evaluation of verification completeness. ASP-DAC 2005: 323-326
9		Wen-Tsan Hsieh, Chih-Chieh Shiue, Chien-Nan Jimmy Liu: A novel approach for high-level power modeling of sequential circuits using recurrent neural networks. ISCAS (4) 2005: 3591-3594
8		Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing Ya Jou: Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs. ISCAS (6) 2005: 5682-5685
	2004
7		Chin-Lung Chuang, Dong-Jung Lu, Chien-Nan Jimmy Liu: A Snapshot Method to Provide Full Visibility for Functional Debugging Using FPGA. Asian Test Symposium 2004: 164-169
	2003
6		Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou: A Design-for-Verification Technique for Functional Pattern Reduction. IEEE Design & Test of Computers 20(2): 48-55 (2003)
	2002
5		Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou: Effective Error Diagnosis for RTL Designs in HDLs. Asian Test Symposium 2002: 362-367
	2001
4		Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou: An efficient design-for-verification technique for HDLs. ASP-DAC 2001: 103-108
3		Chien-Nan Jimmy Liu, Chia-Chih Yen, Jing-Yang Jou: Automatic Functional Vector Generation Using the Interacting FSM Model. ISQED 2001: 372-377
	2000
2		Chien-Nan Jimmy Liu, Jing-Yang Jou: An Automatic Controller Extractor for HDL Descriptions at the RTL. IEEE Design & Test of Computers 17(3): 72-77 (2000)
	1999
1		Chien-Nan Jimmy Liu, Jing-Yang Jou: An Efficient Functional Coverage Test for HDL Descriptions at RTL. ICCD 1999: 325-327

Coauthor Index

1	Li-Yu Chan	[41]
2	Chia-Jen Chang	[45]
3	Chia-Wei Chang	[44]
4	Kai-Hui Chang	[44]
5	Bor-Sen Chen	[24]
6	Hung-Ming Chen	[21] [22] [23] [25] [33] [42]
7	I-Ling Chen	[4] [6]
8	Tai-Chen Chen	[45]
9	Yen-Lung Chen	[41]
10	Kuo-Hsing Cheng	[27]
11	Wei-Hsiang Cheng	[16] [20]
12	Yi-Fang Chiu	[15] [18]
13	Hong-Zu Chou	[44]
14	Chin-Lung Chuang	[7] [16] [20] [43]
15	Ren-Hong Fu	[40]
16	Kai-Wei Hong	[27]
17	Chiu-Han Hsiao	[44]
18	Wen-Tsan Hsieh	[9] [15] [17] [18]
19	Chia-Ling Hsu	[39]
20	Chih-Yang Hsu	[17]
21	Ching-Ji Huang	[30]
22	Li-Da Huang	[21]
23	Pao-Jen Huang	[45]
24	Jie-Hong Roland Jiang (Jie-Hong R. Jiang)	[44]
25	Tai-Ying Jiang	[5] [8] [10] [19] [32]
26	Jing Ya Jou	[8]
27	Jing-Yang Jou	[1] [2] [3] [4] [5] [6] [10] [17] [19] [32]
28	Chin-Cheng Kuo	[11] [13] [14] [27] [30] [34] [38] [41]
29	Sy-Yen Kuo	[44]
30	Kuo-Sheng Lai	[39]
31	Bore-Kuen Lee	[24]
32	Meng-Jung Lee	[30]
33	Mu-Shun Matt Lee	[26] [37] [39] [46]
34	Tsu-Tian Lee	[24]
35	Hsiu-Wen Li	[40]
36	Wei-Ting Liao	[46]
37	Chin-Hsun Lin	[26]
38	Pei-Syun Lin	[34]
39	Shih-Che Lin	[26]
40	Chao-Hung Lu	[21] [22] [23] [25] [33] [42]
41	Dong-Jung Lu	[7] [20]
42	Hungwen Lu	[29] [31]
43	Hsin-Yu Luo	[40]
44	Wen-Yu Shih	[33]
45	Chih-Chieh Shiue	[9]
46	Chauchin Su	[12] [24] [28] [29] [31] [35] [36]
47	I-Ching Tsai	[41]
48	Yu-Chang Tsai	[27]
49	Wenliang Tseng	[12]
50	Yuhwai Tseng	[28] [35] [36]
51	Chih-Hu Wang	[24]
52	Hsin-Wen Wang	[29]
53	Yu-Chien Wang	[11] [13]
54	Wei-Ting Wei	[21]
55	Chi-Yi Yeh	[21]
56	Chia-Chih Yen	[3]
57	Chi-Chia Yu	[15] [18]

Colors in the list of coauthors

Last update Sun Jun 3 16:06:10 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page