Scott Little

	2011
16		Scott Little, David Walter, Chris J. Myers, Robert Thacker, Satish Batchu, Tomohiro Yoneda: Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets. IEEE Trans. on CAD of Integrated Circuits and Systems 30(4): 617-630 (2011)
	2010
15		John Havlicek, Scott Little, Oded Maler, Dejan Nickovic: Property-Based Monitoring of Analog and Mixed-Signal Systems. FORMATS 2010: 23-24
14		Scott Little, David Walter, Kevin Jones, Chris J. Myers, Alper Sen: Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces. Int. J. Found. Comput. Sci. 21(2): 191-210 (2010)
	2009
13		Robert Thacker, Chris J. Myers, Kevin Jones, Scott Little: A new verification method for embedded systems. ICCD 2009: 193-200
	2008
12		David Walter, Scott Little, Chris J. Myers, Nicholas Seegmiller, Tomohiro Yoneda: Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2223-2235 (2008)
	2007
11		David Walter, Scott Little, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda: Symbolic Model Checking of Analog/Mixed-Signal Circuits. ASP-DAC 2007: 316-323
10		Scott Little, David Walter, Kevin Jones, Chris J. Myers: Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces. ATVA 2007: 114-128
9		David Walter, Scott Little, Chris J. Myers: Bounded Model Checking of Analog and Mixed-Signal Circuits Using an SMT Solver. ATVA 2007: 66-81
8		Scott Little, Alper Sen, Chris J. Myers: Application of Automated Model Generation Techniques to Analog/Mixed-Signal Circuits. MTV 2007: 109-115
	2006
7		Scott Little, Nicholas Seegmiller, David Walter, Chris J. Myers, Tomohiro Yoneda: Verification of analog/mixed-signal circuits using labeled hybrid petri nets. ICCAD 2006: 275-282
6		Chris J. Myers, Reid R. Harrison, David Walter, Nicholas Seegmiller, Scott Little: The Case for Analog Circuit Verification. Electr. Notes Theor. Comput. Sci. 153(3): 53-63 (2006)
5		Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda: Verification of timed circuits with failure-directed abstractions. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 403-412 (2006)
	2004
4		Scott Little, David Walter, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda: Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets. ATVA 2004: 426-440
	2003
3		Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda: Verification of Timed Circuits with Failure Directed Abstractions. ICCD 2003: 28-35
	2001
2		Chris Winstead, Jie Dai, Woo Jin Kim, Scott Little, Yong-Bin Kim, Chris J. Myers, Christian Schlegel: Analog MAP Decoder for (8, 4) Hamming Code in Subthreshold CMOS. ARVLSI 2001: 132-147
1		Martin Van De Bovenkamp, Ruben Jongkind, Gu Van Rhijn, Frans M. van Eijnatten, Gudela Grote, Jouni Lehtelä, Timo Leskinen, Peter Vink, Scott Little, Toni Wäfler: The E/S Tool IT-Support for Ergonomic and Sociotechnical System Design. ER (Workshops) 2001: 67-80

Coauthor Index

1	Satish Batchu	[16]
2	Martin Van De Bovenkamp	[1]
3	Jie Dai	[2]
4	Frans M. van Eijnatten	[1]
5	Gudela Grote	[1]
6	Reid R. Harrison	[6]
7	John Havlicek	[15]
8	Kevin Jones	[10] [13] [14]
9	Ruben Jongkind	[1]
10	Woo Jin Kim	[2]
11	Yong-Bin Kim	[2]
12	Jouni Lehtelä	[1]
13	Timo Leskinen	[1]
14	Oded Maler	[15]
15	Chris J. Myers	[2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [16]
16	Dejan Nickovic	[15]
17	Gu Van Rhijn	[1]
18	Christian Schlegel	[2]
19	Nicholas Seegmiller	[4] [6] [7] [11] [12]
20	Alper Sen	[8] [14]
21	Robert Thacker	[13] [16]
22	Peter Vink	[1]
23	Toni Wäfler	[1]
24	David Walter	[3] [4] [5] [6] [7] [9] [10] [11] [12] [14] [16]
25	Chris Winstead	[2]
26	Tomohiro Yoneda	[3] [4] [5] [7] [11] [12] [16]
27	Hao Zheng (Hank Jayne)	[3] [5]

Colors in the list of coauthors

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