 | 2010 |
|---|
| 7 |       | Chun-Cheng Liu,
Soon-Jyh Chang,
Guan-Ying Huang,
Ying-Zu Lin,
Chung-Ming Huang,
Chih-Hao Huang,
Linkai Bu,
Chih-Chung Tsai:
A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation.
ISSCC 2010: 386-387 |
| 6 | | Ying-Zu Lin,
Cheng-Wu Lin,
Soon-Jyh Chang:
A 5-bit 3.2-GS/s Flash ADC With a Digital Offset Calibration Scheme.
IEEE Trans. VLSI Syst. 18(3): 509-513 (2010) |
| 5 | | Ying-Zu Lin,
Soon-Jyh Chang,
Yen-Ting Liu,
Chun-Cheng Liu,
Guan-Ying Huang:
An Asynchronous Binary-Search ADC Architecture With a Reduced Comparator Count.
IEEE Trans. on Circuits and Systems 57-I(8): 1829-1837 (2010) |
| 4 | | Chun-Cheng Liu,
Soon-Jyh Chang,
Guan-Ying Huang,
Ying-Zu Lin:
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure.
J. Solid-State Circuits 45(4): 731-740 (2010) |
| 2009 |
|---|
| 3 | | Ying-Zu Lin,
Soon-Jyh Chang,
Yen-Ting Liu,
Chun-Cheng Liu,
Guan-Ying Huang:
A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS.
ISSCC 2009: 80-81 |
| 2 | | Ying-Zu Lin,
Soon-Jyh Chang,
Yen-Ting Liu:
A 5-bit 4.2-GS/s Flash ADC in 0.13-µm CMOS Process.
IEICE Transactions 92-C(2): 258-268 (2009) |
| 2008 |
|---|
| 1 | | Soon-Jyh Chang,
Ying-Zu Lin,
Yen-Ting Liu:
A Digitally Calibrated CMOS Transconductor With a 100-MHz Bandwidth and 75-dB SFDR.
IEEE Trans. on Circuits and Systems 55-II(11): 1089-1093 (2008) |
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