Xijiang Lin

	2011
33		Xijiang Lin, Elham K. Moghaddam, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jerzy Tyszer: Power Aware Embedded Test. Asian Test Symposium 2011: 511-516
	2010
32		Xijiang Lin, Janusz Rajski: Adaptive Low Shift Power Test Pattern Generator for Logic BIST. Asian Test Symposium 2010: 355-360
31		Tom Waayers, Richard Morren, Xijiang Lin, Mark Kassab: Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains. ITC 2010: 114-123
30		Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab: Low capture power at-speed test in EDT environment. ITC 2010: 714-723
29		Dat Tran, LeRoy Winemberg, Darrell Carder, Xijiang Lin, Joe LeBritton, Bruce Swanson: Detecting and diagnosing open defects. ITC 2010: 811
28		Elif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak: On Reducing Scan Shift Activity at RTL. IEEE Trans. on CAD of Integrated Circuits and Systems 29(7): 1110-1120 (2010)
	2009
27		Xijiang Lin, Mark Kassab: Test Generation for Designs with On-Chip Clock Generators. Asian Test Symposium 2009: 411-417
26		Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer: Low-Power Scan Operation in Test Compression Environment. IEEE Trans. on CAD of Integrated Circuits and Systems 28(11): 1742-1755 (2009)
	2008
25		Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer: Low Power Scan Shift and Capture in the EDT Environment. ITC 2008: 1-10
24		Xijiang Lin, Janusz Rajski: Test Generation for Interconnect Opens. ITC 2008: 1-7
23		Elif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak: Reducing Scan Shift Power at RTL. VTS 2008: 139-146
22		Xijiang Lin, Yu Huang: Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells. J. Electronic Testing 24(4): 327-334 (2008)
	2007
21		Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski: Low Shift and Capture Power Scan Tests. VLSI Design 2007: 793-798
20		Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron Press: Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality CoRR abs/0710.4763: (2007)
19		Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski: Scan-Based Tests with Low Switching Activity. IEEE Design & Test of Computers 24(3): 268-275 (2007)
	2006
18		Santiago Remersaro, Xijiang Lin, Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski: Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs. ITC 2006: 1-10
17		Xijiang Lin, Janusz Rajski: The Impacts of Untestable Defects on Transition Fault Testing. VTS 2006: 2-7
16		Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski: Scan Tests with Multiple Fault Activation Cycles for Delay Faults. VTS 2006: 343-348
	2005
15		Xijiang Lin, Janusz Rajski: Propagation delay fault: a new fault model to test delay faults. ASP-DAC 2005: 178-183
14		Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron Press: Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality. DATE 2005: 56-61
13		Matthias Beck, Olivier Barondeau, Frank Poehl, Xijiang Lin, Ron Press: Measures to Improve Delay Fault Testing on Low-Cost Testers - A Case Study. VTS 2005: 223-228
	2003
12		Xijiang Lin, Rob Thompson: Test generation for designs with multiple clocks. DAC 2003: 662-667
11		Xijiang Lin, Ron Press, Janusz Rajski, Paul Reuter, Thomas Rinderknecht, Bruce Swanson, Nagesh Tamarapalli: High-Frequency, At-Speed Scan Testing. IEEE Design & Test of Computers 20(5): 17-25 (2003)
	2002
10		Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski: Conflict driven techniques for improving deterministic test pattern generation. ICCAD 2002: 87-93
9		Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich: Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture. VTS 2002: 3-8
	2001
8		Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin: Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with Scan. Asian Test Symposium 2001: 467
7		Xijiang Lin, Janusz Rajski, Irith Pomeranz, Sudhakar M. Reddy: On static test compaction and test pattern ordering for scan designs. ITC 2001: 1088-1097
	2000
6		Xijiang Lin, Wu-Tung Cheng, Irith Pomeranz, Sudhakar M. Reddy: SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration. VTS 2000: 205-212
	1999
5		Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy: Full Scan Fault Coverage With Partial Scan. DATE 1999: 468-472
4		Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy: Techniques for improving the efficiency of sequential circuit test generation. ICCAD 1999: 147-151
3		Sudhakar M. Reddy, Irith Pomeranz, Nadir Z. Basturkmen, Xijiang Lin: Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits. VTS 1999: 275-283
	1998
2		Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy: MIX: A Test Generation System for Synchronous Sequential Circuits. VLSI Design 1998: 456-463
1		Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy: On Removing Redundant Faults in Synchronous Sequential Circuits. VTS 1998: 168-175

Coauthor Index

1	Greg Aldrich	[9]
2	Elif Alpaslan	[23] [28]
3	Olivier Barondeau	[13] [14] [20]
4	Nadir Z. Basturkmen	[3]
5	Matthias Beck	[13] [14] [20]
6	Darrell Carder	[29]
7	Wu-Tung Cheng	[6] [23] [28]
8	Dariusz Czysz	[25] [26]
9	Jennifer Dworak	[23] [28]
10	Yu Huang	[22] [23] [28]
11	Martin Kaibel	[14] [20]
12	Mark Kassab	[25] [26] [27] [30] [31]
13	Joe LeBritton	[29]
14	Elham K. Moghaddam	[30] [33]
15	Richard Morren	[31]
16	Grzegorz Mrugalski	[25] [26]
17	Nilanjan Mukherjee	[30] [33]
18	Benoit Nadeau-Dostie	[33]
19	Frank Poehl	[13] [14] [20]
20	Irith Pomeranz	[1] [2] [3] [4] [5] [6] [7] [8] [10] [16] [18] [19] [21]
21	Ron Press	[11] [13] [14] [20]
22	Rajesh Raina	[9]
23	Janusz Rajski	[7] [10] [11] [15] [16] [17] [18] [19] [21] [24] [25] [26] [30] [32] [33]
24	Sudhakar M. Reddy	[1] [2] [3] [4] [5] [6] [7] [8] [10] [16] [18] [19] [21] [30]
25	Santiago Remersaro	[18] [19] [21]
26	Paul Reuter	[11]
27	Thomas Rinderknecht	[11]
28	Bruce Swanson	[9] [11] [29]
29	Nagesh Tamarapalli	[11]
30	Nandu Tendolkar	[9]
31	Rob Thompson	[12]
32	Dat Tran	[29]
33	Jerzy Tyszer	[25] [26] [33]
34	Tom Waayers	[31]
35	Chen Wang	[10]
36	LeRoy Winemberg	[29]
37	Rick Woltenberg	[9]
38	Zhuo Zhang	[16] [18]

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