 | 2011 |
|---|
| 6 |       | Jin-Fu Lin,
Soon-Jyh Chang,
Te-Chieh Kung,
Hsin-Wen Ting,
Chih-Hao Huang:
Transition-Code Based Linearity Test Method for Pipelined ADCs With Digital Error Correction.
IEEE Trans. VLSI Syst. 19(12): 2158-2169 (2011) |
| 5 | | Jin-Fu Lin,
Soon-Jyh Chang:
A Low-Power Mixed-Architecture ADC with Time-Interleaved Correlated Double Sampling Technique and Power-Efficient Back-End Stages.
IEICE Transactions 94-C(1): 89-101 (2011) |
| 4 | | Jin-Fu Lin,
Hsin-Wen Ting:
Digital Design-for-Diagnosis Method for Error Identification of Pipelined ADCs.
J. Electronic Testing 27(6): 697-709 (2011) |
| 2010 |
|---|
| 3 | | Jin-Fu Lin,
Soon-Jyh Chang,
Chun-Cheng Liu,
Chih-Hao Huang:
A 10-bit 60-MS/s Low-Power Pipelined ADC With Split-Capacitor CDS Technique.
IEEE Trans. on Circuits and Systems 57-II(3): 163-167 (2010) |
| 2009 |
|---|
| 2 | | Jin-Fu Lin,
Soon-Jyh Chang,
Chih-Hao Huang:
Design-for-Test Circuit for the Reduced Code Based Linearity Test Method in Pipelined ADCs with Digital Error Correction Technique.
Asian Test Symposium 2009: 57-62 |
| 2006 |
|---|
| 1 | | Jin-Fu Lin,
Soon-Jyh Chang:
A high speed pipelined analog-to-digital converter using modified time-shifted correlated double sampling technique.
ISCAS 2006 |
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