 | 2012 |
| 22 |  | Jai-Ming Lin,
Wei-Yi Cheng,
Chung-Lin Lee,
Richard C. Hsu:
Voltage island-driven floorplanning considering level shifter placement.
ASP-DAC 2012: 443-448 |
| 21 |  | Cheng-Wu Lin,
Cheng-Chung Lu,
Jai-Ming Lin,
Soon-Jyh Chang:
Routability-driven placement algorithm for analog integrated circuits.
ISPD 2012: 71-78 |
| 20 |  | Jai-Ming Lin,
Zhi-Xiong Hung:
SKB-Tree: A Fixed-Outline Driven Representation for Modern Floorplanning Problems.
IEEE Trans. VLSI Syst. 20(3): 473-484 (2012) |
| 2011 |
| 19 |  | Jia-Ru Chuang,
Jai-Ming Lin:
Efficient multi-layer obstacle-avoiding preferred direction rectilinear Steiner tree construction.
ASP-DAC 2011: 527-532 |
| 18 |  | Cheng-Wu Lin,
Jai-Ming Lin,
Yen-Chih Chiu,
Chun-Po Huang,
Soon-Jyh Chang:
Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits.
DAC 2011: 528-533 |
| 17 |  | Jai-Ming Lin,
Zhi-Xiong Hung:
UFO: Unified Convex Optimization Algorithms for Fixed-Outline Floorplanning Considering Pre-Placed Modules.
IEEE Trans. on CAD of Integrated Circuits and Systems 30(7): 1034-1044 (2011) |
| 2010 |
| 16 |  | Jai-Ming Lin,
Hsi Hung:
UFO: unified convex optimization algorithms for fixed-outline floorplanning.
ASP-DAC 2010: 555-560 |
| 15 |  | Cheng-Wu Lin,
Jai-Ming Lin,
Chun-Po Huang,
Soon-Jyh Chang:
Performance-driven analog placement considering boundary constraint.
DAC 2010: 292-297 |
| 2005 |
| 14 |  | Jai-Ming Lin,
Guang-Ming Wu,
Yao-Wen Chang,
Jen-Hui Chuang:
Placement with symmetry constraints for analog layout design using TCG-S.
ASP-DAC 2005: 1135-1137 |
| 13 |  | Jai-Ming Lin,
Yao-Wen Chang:
TCG: A transitive closure graph-based representation for general floorplans.
IEEE Trans. VLSI Syst. 13(2): 288-292 (2005) |
| 2004 |
| 12 |  | Jai-Ming Lin,
Yao-Wen Chang:
TCG-S: orthogonal coupling of P/sup */-admissible representations for general floorplans.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(6): 968-980 (2004) |
| 2003 |
| 11 |  | Jai-Ming Lin,
Yao-Wen Chang,
Shih-Ping Lin:
Corner sequence - a P-admissible floorplan representation with a worst case linear-time packing scheme.
IEEE Trans. VLSI Syst. 11(4): 679-686 (2003) |
| 2002 |
| 10 |  | Jai-Ming Lin,
Yao-Wen Chang:
TCG-S: orthogonal coupling of P*-admissible representations for general floorplans.
DAC 2002: 842-847 |
| 9 |  | Jai-Ming Lin,
Hsin-Lung Chen,
Yao-Wen Chang:
Arbitrary Convex and Concave Rectilinear Module Packing Using TCG.
DATE 2002: 69-75 |
| 8 |  | Guang-Ming Wu,
Jai-Ming Lin,
Yao-Wen Chang:
Performance-driven placement for dynamically reconfigurable FPGAs.
ACM Trans. Design Autom. Electr. Syst. 7(4): 628-642 (2002) |
| 7 |  | Jai-Ming Lin,
Hsin-Lung Chen,
Yao-Wen Chang:
Arbitrarily shaped rectilinear module placement using the transitive closure graph representation.
IEEE Trans. VLSI Syst. 10(6): 886-901 (2002) |
| 2001 |
| 6 |  | Jai-Ming Lin,
Yao-Wen Chang:
TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans.
DAC 2001: 764-769 |
| 5 |  | Guang-Ming Wu,
Jai-Ming Lin,
Mango Chia-Tso Chao,
Yao-Wen Chang:
Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning.
ICCD 2001: 335-347 |
| 4 |  | Guang-Ming Wu,
Jai-Ming Lin,
Yao-Wen Chang:
An Algorithm for Dynamically Reconfigurable FPGA Placement.
ICCD 2001: 501-504 |
| 3 |  | Guang-Ming Wu,
Jai-Ming Lin,
Yao-Wen Chang:
Generic ILP-based approaches for time-multiplexed FPGA partitioning.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(10): 1266-1274 (2001) |
| 2 |  | Yao-Wen Chang,
Jai-Ming Lin,
Martin D. F. Wong:
Matching-based algorithm for FPGA channel segmentation design.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(6): 784-791 (2001) |
| 1998 |
| 1 |  | Yao-Wen Chang,
Jai-Ming Lin,
D. F. Wong:
Graph matching-based algorithms for FPGA segmentation design.
ICCAD 1998: 34-39 |