 | 2010 |
|---|
| 7 |       | Tsung-Yi Wu,
Tzi-Wei Kao,
Shi-Yi Huang,
Tai-Lun Li,
How-Rern Lin:
Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs.
ASP-DAC 2010: 444-449 |
| 6 | | Tsung-Yi Wu,
Tzi-Wei Kao,
How-Rern Lin:
Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC/NoC Designs.
IEICE Transactions 93-A(12): 2581-2589 (2010) |
| 2009 |
|---|
| 5 | | How-Rern Lin,
Wei-Hao Chiu,
Tsung-Yi Wu:
A Conditional Isolation Technique for Low-Energy and High-Performance Wide Domino Gates.
IEICE Transactions 92-C(4): 386-390 (2009) |
| 1999 |
|---|
| 4 | | How-Rern Lin,
TingTing Hwang:
On determining sensitization criterion in an iterative gate sizing process.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(2): 231-238 (1999) |
| 1995 |
|---|
| 3 | | How-Rern Lin,
TingTing Hwang:
Power recduction by gate sizing with path-oriented slack calculation.
ASP-DAC 1995 |
| 1994 |
|---|
| 2 |  | How-Rern Lin,
Ching-Lung Chou,
Yu-Chin Hsu,
TingTing Hwang:
Cell Height Driven Transistor Sizing in a Cell Based Module Design.
EDAC-ETC-EUROASIC 1994: 425-429 |
| 1 | | How-Rern Lin,
TingTing Hwang:
Dynamical identification of critical paths for iterative gate sizing.
ICCAD 1994: 481-484 |
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