 | 2011 |
|---|
| 8 |       | Fanta Chen,
Min-Sheng Kao,
Yu-Hao Hsu,
Chih-Hsing Lin,
Jen-Ming Wu,
Ching-Te Chiu,
Shuo-Hung Hsu:
A 10 to 11.5GHz rotational phase and frequency detector for clock recovery circuit.
ISCAS 2011: 185-188 |
| 7 | | Wen-Chih Huang,
Chih-Hsing Lin,
Ching-Te Chiu:
Embedded transition inversion coding for low power serial link.
SiPS 2011: 102-105 |
| 2010 |
|---|
| 6 | | Chih-Hsing Lin,
Jia Shiuan Tsai,
Ching-Te Chiu:
Switching bilateral filter with a texture/noise detector for universal noise removal.
ICASSP 2010: 1434-1437 |
| 5 | | Chih-Hsing Lin,
Yung-Chang Chang,
Wen-Chih Huang,
Wei-Chih Lai,
Ching-Te Chiu,
Jen-Ming Wu,
Shuo-Hung Hsu,
Chun-Ming Huang,
Chih-Chyau Yang,
Shih-Lun Chen:
A packet-based emulating platform with serializer/deserializer interface for heterogeneous IP verification.
ISCAS 2010: 1061-1064 |
| 4 | | Chih-Hsing Lin,
Jia Shiuan Tsai,
Ching-Te Chiu:
Switching Bilateral Filter With a Texture/Noise Detector for Universal Noise Removal.
IEEE Transactions on Image Processing 19(9): 2307-2320 (2010) |
| 2009 |
|---|
| 3 | | Min-Sheng Kao,
Jen-Ming Wu,
Chih-Hsing Lin,
Fanta Chen,
Ching-Te Chiu,
Shawn S. H. Hsu:
A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18- $\mu$ m CMOS Technology.
IEEE Trans. VLSI Syst. 17(5): 688-696 (2009) |
| 2008 |
|---|
| 2 | | Yu-Hao Hsu,
Ming-Hao Lu,
Ping-Ling Yang,
Fanta Chen,
You-Hung Li,
Min-Sheng Kao,
Chih-Hsing Lin,
Ching-Te Chiu,
Jen-Ming Wu,
Shuo-Hung Hsu,
Yarsun Hsu:
A 28Gbps 4×4 switch with low jitter SerDes using area-saving RF model in 0.13µm CMOS technology.
ISCAS 2008: 3086-3089 |
| 2007 |
|---|
| 1 | | Chih-Hsing Lin,
Ching-Te Chiu:
A 2.24GHz Wide Range Low Jitter DLL-Based Frequency Multiplier using PMOS Active Load for Communication Applications.
ISCAS 2007: 3888-3891 |
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