 | 2010 |
|---|
| 9 |       | Cheng-Chi Wong,
Ming-Wei Lai,
Chien-Ching Lin,
Hsie-Chia Chang,
Chen-Yi Lee:
Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture.
J. Solid-State Circuits 45(2): 422-432 (2010) |
| 2009 |
|---|
| 8 | | Hsie-Chia Chang,
Chien-Ching Lin,
Fu-Ke Chang,
Chen-Yi Lee:
A Universal VLSI Architecture for Reed-Solomon Error-and-Erasure Decoders.
IEEE Trans. on Circuits and Systems 56-I(9): 1960-1967 (2009) |
| 7 | | Chih-Hao Liu,
Chien-Ching Lin,
Shao-Wei Yen,
Chih-Lung Chen,
Hsie-Chia Chang,
Chen-Yi Lee,
Yar-Sun Hsu,
Shyh-Jye Jou:
Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network.
IEEE Trans. on Circuits and Systems 56-II(9): 734-738 (2009) |
| 2008 |
|---|
| 6 | | Chih-Hao Liu,
Chien-Ching Lin,
Hsie-Chia Chang,
Chen-Yi Lee,
Yarsun Hsua:
Multi-mode message passing switch networks applied for QC-LDPC decoder.
ISCAS 2008: 752-755 |
| 2007 |
|---|
| 5 | | Yen-Chin Liao,
Chien-Ching Lin,
Hsie-Chia Chang,
Chih-Wei Liu:
Self-Compensation Technique for Simplified Belief-Propagation Algorithm.
IEEE Transactions on Signal Processing 55(6-2): 3061-3072 (2007) |
| 4 | | Terng-Ren Hsu,
Chien-Ching Lin,
Terng-Yin Hsu,
Chen-Yi Lee:
MLP/BP-Based Soft Decision Feedback Equalization with Bit-Interleaved TCM for Wireless Applications.
IEICE Transactions 90-A(4): 879-884 (2007) |
| 2006 |
|---|
| 3 | | Chien-Ching Lin,
Y.-H. Shih,
Hsie-Chia Chang,
Chen-Yi Lee:
A low power turbo/Viterbi decoder for 3GPP2 applications.
IEEE Trans. VLSI Syst. 14(4): 426-430 (2006) |
| 2004 |
|---|
| 2 |  | Yi-Chen Tseng,
Chien-Ching Lin,
Hsie-Chia Chang,
Chen-Yi Lee:
A power and area efficient multi-mode FEC processor.
ISCAS (2) 2004: 253-256 |
| 1 | | Hsie-Chia Chang,
Chien-Ching Lin,
Tien-Yuan Hsiao,
Jieh-Tsorng Wu,
Ta-Hui Wang:
Multi-level memory systems using error control codes.
ISCAS (2) 2004: 393-396 |
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