Chi-Sheng Lin

	2012
14		Jia-Chin Lin, Chi-Sheng Lin, Chih-Neng Liang, Bo-Chiuan Chen: Wireless communication performance based on IEEE 802.11p R2V field trials. IEEE Communications Magazine 50(5): 184-191 (2012)
	2011
13		Tsung-Che Lu, Lan-Da Van, Chi-Sheng Lin, Chun-Ming Huang: A 0.5V 1KS/s 2.5nW 8.52-ENOB 6.8fJ/conversion-step SAR ADC for biomedical applications. CICC 2011: 1-4
12		Chi-Sheng Lin, Ting-Hsu Chien, Chin-Long Wey: A 5.5-GHz 1-mW Full-Modulus-Range Programmable Frequency Divider in 90-nm CMOS Process. IEEE Trans. on Circuits and Systems 58-II(9): 550-554 (2011)
	2010
11		Chi-Sheng Lin, Jia-Chin Lin: Improved time-domain channel estimation techniques in IEEE 802.11p environments. CSNDSP 2010: 437-442
10		Chi-Sheng Lin, Ting-Hsu Chien, Chin-Long Wey: An effective phase detector for phase-locked loops with wide capture range and fast acquisition time. ISCAS 2010: 1843-1846
9		Ting-Hsu Chien, Chi-Sheng Lin, Chin-Long Wey, Ying-Zong Juang, Chun-Ming Huang: High-speed and low-power programmable frequency divider. ISCAS 2010: 4301-4304
8		Chi-Sheng Lin, Jia-Chin Lin: Novel Channel Estimation Techniques in IEEE 802.11p Environments. VTC Spring 2010: 1-5
	2009
7		Chi-Sheng Lin, Che-Kang Sun, Jia-Chin Lin, Bo-Chiuan Chen: Performance evaluations of channel estimations in IEEE 802.11p environments. ICUMT 2009: 1-5
6		Ting-Hsu Chien, Chi-Sheng Lin, Ying-Zong Juang, Chun-Ming Huang, Chin-Long Wey: An edge-missing compensator for fast-settling wide-locking-range PLLs. ISSCC 2009: 394-395
	2006
5		Ruei-Jhe Tsai, Hsin-Wen Ting, Chi-Sheng Lin, Bin-Da Liu: A CAM/WTA-Based High Speed and Low Power Longest Prefix Matching Circuit Design. APCCAS 2006: 426-429
	2004
4		Hui-Chin Tseng, Hsin-Hung Ou, Chi-Sheng Lin, Bin-Da Liu: A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach. ISLPED 2004: 252-256
	2003
3		Chi-Sheng Lin, Kuan-Hua Chen, Bin-Da Liu: Low-power and low-voltage fully parallel content-addressable memory. ISCAS (5) 2003: 373-376
	2002
2		Shin-Hong Ou, Chi-Sheng Lin, Bin-Da Liu: A scalable sorting architecture based on maskable WTA/MAX circuit. ISCAS (4) 2002: 209-212
1		Chi-Sheng Lin, Bin-Da Liu: Design of a pipelined and expandable sorting architecture with simple control scheme. ISCAS (4) 2002: 217-220

Coauthor Index

1	Bo-Chiuan Chen	[7] [14]
2	Kuan-Hua Chen	[3]
3	Ting-Hsu Chien	[6] [9] [10] [12]
4	Chun-Ming Huang	[6] [9] [13]
5	Ying-Zong Juang	[6] [9]
6	Chih-Neng Liang	[14]
7	Jia-Chin Lin	[7] [8] [11] [14]
8	Bin-Da Liu	[1] [2] [3] [4] [5]
9	Tsung-Che Lu	[13]
10	Hsin-Hung Ou	[4]
11	Shin-Hong Ou	[2]
12	Che-Kang Sun	[7]
13	Hsin-Wen Ting	[5]
14	Ruei-Jhe Tsai	[5]
15	Hui-Chin Tseng	[4]
16	Lan-Da Van	[13]
17	Chin-Long Wey	[6] [9] [10] [12]

Colors in the list of coauthors

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