Cheng-Hung Lin

	2012
18		Cheng-Hung Lin, Chen-Hsiung Liu, Shih-Chieh Chang, Wing-Kai Hon: Memory-efficient pattern matching architectures using perfect hashing on graphic processing units. INFOCOM 2012: 1978-1986
	2011
17		Cheng-Hung Lin, Chen-Hsiung Liu, Shih-Chieh Chang: Accelerating Regular Expression Matching Using Hierarchical Parallel Machines on GPU. GLOBECOM 2011: 1-5
16		Cheng-Hung Lin, Shih-Chieh Chang: Efficient Pattern Matching Algorithm for Memory Architecture. IEEE Trans. VLSI Syst. 19(1): 33-41 (2011)
15		Cheng-Hung Lin, Chun-Yu Chen, An-Yeu Wu: Area-Efficient Scalable MAP Processor Design for High-Throughput Multistandard Convolutional Turbo Decoding. IEEE Trans. VLSI Syst. 19(2): 305-318 (2011)
	2010
14		Cheng-Hung Lin, Sheng-Yu Tsai, Chen-Hsiung Liu, Shih-Chieh Chang, Jyuo-Min Shyu: Accelerating String Matching Using Multi-Threaded Algorithm on GPU. GLOBECOM 2010: 1-5
	2009
13		Cheng-Hung Lin, Hsien-Sheng Hsiao: Hierarchical state machine architecture for regular expression pattern matching. ACM Great Lakes Symposium on VLSI 2009: 133-136
12		Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, An-Yeu Wu: A 52-mW 8.29mm2 19-mode LDPC decoder chip for mobile WiMAX applications. ASP-DAC 2009: 121-122
11		Cheng-Hung Lin, Chun-Yu Chen, Tsung-Han Tsai, An-Yeu Wu: Low-Power Memory-Reduced Traceback MAP Decoding for Double-Binary Convolutional Turbo Decoder. IEEE Trans. on Circuits and Systems 56-I(5): 1005-1016 (2009)
	2008
10		Cheng-Hung Lin, Chun-Yu Chen, An-Yeu Wu: Low-power traceback MAP decoding for double-binary convolutional turbo decoder. ISCAS 2008: 736-739
9		Chun-Yu Chen, Cheng-Hung Lin, An-Yeu Wu: High-throughput dual-mode single/double binary map processor design for wireless wan. SiPS 2008: 83-87
8		Fan-Min Li, Cheng-Hung Lin, An-Yeu Wu: Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel. IEEE Trans. VLSI Syst. 16(10): 1358-1371 (2008)
	2007
7		Cheng-Hung Lin, Yu-Tang Tai, Shih-Chieh Chang: Optimization of pattern matching algorithm for memory based architecture. ANCS 2007: 11-16
6		Yu-Min Kuo, Cheng-Hung Lin, Chun-Yao Wang, Shih-Chieh Chang, Pei-Hsin Ho: Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure. ISQED 2007: 344-349
5		Cheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang, Shih-Chieh Chang: Optimization of Pattern Matching Circuits for Regular Expression on FPGA. IEEE Trans. VLSI Syst. 15(12): 1303-1310 (2007)
	2006
4		Cheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang, Shih-Chieh Chang: Optimization of regular expression pattern matching circuits on FPGA. DATE Designers' Forum 2006: 12-17
3		Fan-Min Li, Cheng-Hung Lin, An-Yeu Wu: A New Early Termination Scheme of Iterative Turbo Decoding Using Decoding Threshold. SiPS 2006: 89-94
	2005
2		Cheng-Hung Lin, Yung-Chang Huang, Shih-Chieh Chang, Wen-Ben Jone: Design and design automation of rectification logic for engineering change. ASP-DAC 2005: 1006-1009
1		Tsung-Han Tsai, Cheng-Hung Lin, An-Yeu Wu: A memory-reduced log-MAP kernel for turbo decoder. ISCAS (2) 2005: 1032-1035

Coauthor Index

1	Shih-Chieh Chang	[2] [4] [5] [6] [7] [14] [16] [17] [18]
2	Chun-Yu Chen	[9] [10] [11] [15]
3	Pei-Hsin Ho	[6]
4	Wing-Kai Hon	[18]
5	Hsien-Sheng Hsiao	[13]
6	Chih-Tsun Huang	[4] [5]
7	Yung-Chang Huang	[2]
8	Chang-Ping Jiang	[4] [5]
9	Wen-Ben Jone	[2]
10	Yu-Min Kuo	[6]
11	Fan-Min Li	[3] [8]
12	Chen-Hsiung Liu	[14] [17] [18]
13	Xin-Yu Shih	[12]
14	Jyuo-Min Shyu	[14]
15	Yu-Tang Tai	[7]
16	Sheng-Yu Tsai	[14]
17	Tsung-Han Tsai	[1] [11]
18	Chun-Yao Wang	[6]
19	An-Yeu Wu	[1] [3] [8] [9] [10] [11] [12] [15]
20	Cheng-Zhou Zhan	[12]

Colors in the list of coauthors

Last update Mon Jun 4 20:40:43 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page