Chang-Tzu Lin

	2012
9		Chieh-Jui Lee, Shih-Ying Liu, Chuan-Chia Huang, Hung-Ming Chen, Chang-Tzu Lin, Chia-Hsin Lee: Hierarchical power network synthesis for multiple power domain designs. ISQED 2012: 477-482
	2011
8		Ding-Ming Kwai, Chang-Tzu Lin: 3D Stacked IC layout considering bond pad density and doubling for manufacturing yield improvement. ISQED 2011: 129-134
	2010
7		Chang-Tzu Lin, Ding-Ming Kwai, Yung-Fa Chou, Ting-Sheng Chen, Wen Ching Wu: CAD reference flow for 3D via-last integrated circuits. ASP-DAC 2010: 187-192
	2007
6		Chang-Tzu Lin, Tai-Wei Kung, De-Sheng Chen, Yiwen Wang, Ching-Hwa Cheng: Noise-Aware Floorplanning for Fast Power Supply Network Design. ISCAS 2007: 2028-2031
5		De-Sheng Chen, Chang-Tzu Lin, Yiwen Wang, Ching-Hwa Cheng: Fixed-outline floorplanning using robust evolutionary search. Eng. Appl. of AI 20(6): 821-830 (2007)
	2006
4		Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang: Modern Floorplanning with Boundary and Fixed-outline Constraints via Genetic Clustering Algorithm. Journal of Circuits, Systems, and Computers 15(1): 107-128 (2006)
	2005
3		Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang, Hsin-Hsien Ho: Modem floorplanning with abutment and fixed-outline constraints. ISCAS (6) 2005: 6214-6217
	2004
2		Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang: Robust fixed-outline floorplanning through evolutionary search. ASP-DAC 2004: 42-44
	2002
1		Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang: GPE: A New Representation for VLSI Floorplan Problem. ICCD 2002: 42-44

Coauthor Index

1	De-Sheng Chen	[1] [2] [3] [4] [5] [6]
2	Hung-Ming Chen	[9]
3	Ting-Sheng Chen	[7]
4	Ching-Hwa Cheng	[5] [6]
5	Yung-Fa Chou	[7]
6	Hsin-Hsien Ho	[3]
7	Chuan-Chia Huang	[9]
8	Tai-Wei Kung	[6]
9	Ding-Ming Kwai	[7] [8]
10	Chia-Hsin Lee	[9]
11	Chieh-Jui Lee	[9]
12	Shih-Ying Liu	[9]
13	Yiwen Wang	[1] [2] [3] [4] [5] [6]
14	Wen Ching Wu	[7]

Colors in the list of coauthors

Last update Mon Jun 4 20:40:43 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page