Xiaoyao Liang

	2012
16		Guihai Yan, Yingmin Li, Yinhe Han, Xiaowei Li, Minyi Guo, Xiaoyao Liang: AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture. HPCA 2012: 287-298
	2011
15		Guihai Yan, Yinhe Han, Hui Liu, Xiaoyao Liang, Xiaowei Li: MicroFix: Using timing interpolation and delay sensors for power reduction. ACM Trans. Design Autom. Electr. Syst. 16(2): 16 (2011)
	2010
14		Guihai Yan, Xiaoyao Liang, Yinhe Han, Xiaowei Li: Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors. ISCA 2010: 485-496
	2009
13		Kristen Lovin, Benjamin C. Lee, Xiaoyao Liang, David Brooks, Gu-Yeon Wei: Empirical performance models for 3T1D memories. ICCD 2009: 398-403
12		Xiaoyao Liang, Benjamin C. Lee, Gu-Yeon Wei, David Brooks: Design and test strategies for microarchitectural post-fabrication tuning. ICCD 2009: 84-90
11		Guihai Yan, Yinhe Han, Hui Liu, Xiaoyao Liang, Xiaowei Li: MicroFix: exploiting path-grained timing adaptability for improving power-performance efficiency. ISLPED 2009: 395-400
10		Xiaoyao Liang, Gu-Yeon Wei, David Brooks: Revival: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency. IEEE Micro 29(1): 127-138 (2009)
	2008
9		Xiaoyao Liang, Gu-Yeon Wei, David Brooks: ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency. ISCA 2008: 191-202
8		Gu-Yeon Wei, David Brooks, Ali Durlov Khan, Xiaoyao Liang: Instruction-driven clock scheduling with glitch mitigation. ISLPED 2008: 357-362
7		Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks: Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability. IEEE Micro 28(1): 60-68 (2008)
	2007
6		Xiaoyao Liang, Kerem Turgay, David Brooks: Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques. ICCAD 2007: 824-830
5		Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks: Process Variation Tolerant 3T1D-Based Cache Architectures. MICRO 2007: 15-26
	2006
4		Xiaoyao Liang, David Brooks: Microarchitecture parameter selection to optimize system performance under process variation. ICCAD 2006: 429-436
3		Xiaoyao Liang, David Brooks: Mitigating the Impact of Process Variations on Processor Register Files and Execution Units. MICRO 2006: 504-514
	2005
2		Xiaoyao Liang, Akshay Athalye, Sangjin Hong: Equalizing data-path for processing speed determination in block level pipelining. ISCAS (2) 2005: 1646-1649
1		Xiaoyao Liang, Akshay Athalye, Sangjin Hong: Dynamic coarse grain dataflow reconfiguration technique for real-time systems design. ISCAS (4) 2005: 3511-3514

Coauthor Index

1	Akshay Athalye	[1] [2]
2	David Brooks	[3] [4] [5] [6] [7] [8] [9] [10] [12] [13]
3	Ramon Canal	[5] [7]
4	Minyi Guo	[16]
5	Yinhe Han	[11] [14] [15] [16]
6	Sangjin Hong	[1] [2]
7	Ali Durlov Khan	[8]
8	Benjamin C. Lee	[12] [13]
9	Xiaowei Li	[11] [14] [15] [16]
10	Yingmin Li	[16]
11	Hui Liu	[11] [15]
12	Kristen Lovin	[13]
13	Kerem Turgay	[6]
14	Gu-Yeon Wei	[5] [7] [8] [9] [10] [12] [13]
15	Guihai Yan	[11] [14] [15] [16]

Colors in the list of coauthors

Last update Mon Jun 4 20:40:43 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page