Shin-Mao Li

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2008

1 Tso-Bing Juang, Sheng-Hung Chen, Shin-Mao Li: A novel VLSI iterative divider architecture for fast quotient generation. ISCAS 2008: 3358-3361

	2008
1		Tso-Bing Juang, Sheng-Hung Chen, Shin-Mao Li: A novel VLSI iterative divider architecture for fast quotient generation. ISCAS 2008: 3358-3361

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