Jin-Fu Li

	2012
66		Cheng-Wen Wu, Shyue-Kung Lu, Jin-Fu Li: On test and repair of 3D random access memory. ASP-DAC 2012: 744-749
65		Ting-Ju Chen, Jin-Fu Li, Tsu-Wei Tseng: Cost-Efficient Built-In Redundancy Analysis With Optimal Repair Rate for RAMs. IEEE Trans. on CAD of Integrated Circuits and Systems 31(6): 930-940 (2012)
	2011
64		Yu-Jen Huang, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu: A built-in self-test scheme for the post-bond test of TSVs in 3D ICs. VTS 2011: 20-25
63		Tsu-Wei Tseng, Jin-Fu Li: A Low-Cost Built-In Redundancy-Analysis Scheme for Word-Oriented RAMs With 2-D Redundancy. IEEE Trans. VLSI Syst. 19(11): 1983-1995 (2011)
62		Chih-Sheng Hou, Jin-Fu Li, Tsu-Wei Tseng: Memory Built-in Self-Repair Planning Framework for RAMs in SoCs. IEEE Trans. on CAD of Integrated Circuits and Systems 30(11): 1731-1743 (2011)
61		Tsu-Wei Tseng, Jin-Fu Li: SETBIST: An Soft-Error Tolerant Built-In Self-Test Scheme for Random Access Memories. J. Inf. Sci. Eng. 27(2): 643-656 (2011)
	2010
60		Jin-Fu Li, Cheng-Wen Wu: Is 3D integration an opportunity or just a hype? ASP-DAC 2010: 541-543
59		Che-Wei Chou, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu: A Test Integration Methodology for 3D Integrated Circuits. Asian Test Symposium 2010: 377-382
58		Chih-Sheng Hou, Jin-Fu Li, Che-Wei Chou: Test and Repair Scheduling for Built-In Self-Repair RAMs in SOCs. DELTA 2010: 3-7
57		Chun-Chuan Chi, Cheng-Wen Wu, Jin-Fu Li: A low-cost and scalable test architecture for multi-core chips. European Test Symposium 2010: 30-35
56		Yu-Jen Huang, Che-Wei Chou, Jin-Fu Li: A low-cost built-in self-test scheme for an array of memories. European Test Symposium 2010: 75-80
55		Yu-Jen Huang, Yun-Chao You, Jin-Fu Li: Enhanced IEEE 1500 test wrapper for testing small RAMs in SOCs. SoCC 2010: 236-240
54		Tsu-Wei Tseng, Chih-Sheng Hou, Jin-Fu Li: Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area cost. VTS 2010: 21-26
53		Tsu-Wei Tseng, Jin-Fu Li, Chih-Sheng Hou: A Built-in Method to Repair SoC RAMs in Parallel. IEEE Design & Test of Computers 27(6): 46-57 (2010)
52		Jin-Fu Li: Testing Comparison and Delay Faults of TCAMs With Asymmetric Cells. IEEE Trans. VLSI Syst. 18(6): 912-920 (2010)
51		Tsu-Wei Tseng, Jin-Fu Li, Chih-Chiang Hsu: ReBISR: A Reconfigurable Built-In Self-Repair Scheme for Random Access Memories in SOCs. IEEE Trans. VLSI Syst. 18(6): 921-932 (2010)
50		Jin-Fu Li, Tsu-Wei Tseng, Chih-Sheng Hou: Reliability-Enhancement and Self-Repair Schemes for SRAMs With Static and Dynamic Faults. IEEE Trans. VLSI Syst. 18(9): 1361-1366 (2010)
49		Tsu-Wei Tseng, Yu-Jen Huang, Jin-Fu Li: DABISR: A Defect-Aware Built-In Self-Repair Scheme for Single/Multi-Port RAMs in SoCs. IEEE Trans. on CAD of Integrated Circuits and Systems 29(10): 1628-1639 (2010)
48		Jin-Fu Li, Yu-Jen Huang, Yong-Jyun Hu: Testing Random Defect and Process Variation Induced Comparison Faults of TCAMs With Asymmetric Cells. IEEE Trans. on CAD of Integrated Circuits and Systems 29(11): 1843-1847 (2010)
	2009
47		Yu-Jen Huang, Jin-Fu Li: Testability Exploration of 3-D RAMs and CAMs. Asian Test Symposium 2009: 397-402
46		Hsing-Chen Lu, Jin-Fu Li: A Programmable Online/Off-line Built-in Self-test Scheme for RAMs with ECC. ISCAS 2009: 1997-2000
45		Bing-Wei Huang, Jin-Fu Li: Efficient diagnosis algorithms for drowsy SRAMs. ISQED 2009: 276-279
44		Yong-Jyun Hu, Yu-Jen Huang, Jin-Fu Li: Modeling and Testing Comparison Faults of TCAMs with Asymmetric Cells. VTS 2009: 15-20
43		Hsiang-Ning Liu, Yu-Jen Huang, Jin-Fu Li: Memory Built-in Self Test in Multicore Chips with Mesh-Based Networks. IEEE Micro 29(5): 46-55 (2009)
	2008
42		Tsu-Wei Tseng, Jin-Fu Li: A Shared Parallel Built-In Self-Repair Scheme for Random Access Memories in SOCs. ITC 2008: 1-9
41		Hong-Ming Shieh, Jin-Fu Li: A Multi-Code Compression Scheme for Test Time Reduction of System-on-Chip Designs. IEICE Transactions 91-D(10): 2428-2434 (2008)
40		Da-Ming Chang, Jin-Fu Li, Yu-Jen Huang: A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy. J. Electronic Testing 24(1-3): 181-192 (2008)
	2007
39		Jin-Fu Li, Feijun (Frank) Zheng, Kwang-Ting Cheng: Diagnosing scan chains using SAT-based diagnostic pattern generation. SoCC 2007: 273-276
38		Yao-Xian Yang, Jin-Fu Li, Hsiang-Ning Liu, Chin-Long Wey: Design of cost-efficient memory-based FFT processors using single-port memories. SoCC 2007: 29-32
37		Tsu-Wei Tseng, Chun-Hsien Wu, Yu-Jen Huang, Jin-Fu Li, Alex Pao, Kevin Chiu, Eliot Chen: A Built-In Self-Repair Scheme for Multiport RAMs. VTS 2007: 355-360
36		Jin-Fu Li, Tsu-Wei Tseng, Chin-Long Wey: An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories CoRR abs/0710.4747: (2007)
35		Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu: Raisin: Redundancy Analysis Algorithm Simulation. IEEE Design & Test of Computers 24(4): 386-396 (2007)
34		Chao-Da Huang, Jin-Fu Li, Tsu-Wei Tseng: ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips. IEEE Trans. VLSI Syst. 15(10): 1135-1143 (2007)
33		Jin-Fu Li: Transparent-Test Methodologies for Random Access Memories Without/With ECC. IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1888-1893 (2007)
32		Jin-Fu Li: Testing Ternary Content Addressable Memories With Comparison Faults Using March-Like Tests. IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 919-931 (2007)
31		Jin-Fu Li, Chao-Da Huang: An Efficient Diagnosis Scheme for RAMs with Simple Functional Faults. IEICE Transactions 90-A(12): 2703-2711 (2007)
30		Yu-Jen Huang, Jin-Fu Li: Testing ternary content addressable memories with active neighbourhood pattern-sensitive faults. IET Computers & Digital Techniques 1(3): 246-255 (2007)
	2006
29		Tsu-Wei Tseng, Jin-Fu Li, Da-Ming Chang: A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap. DATE 2006: 53-58
28		Yu-Jen Huang, Da-Ming Chang, Jin-Fu Li: A Built-In Redundancy-Analysis Scheme for Self-Repairable RAMs with Two-Level Redundancy. DFT 2006: 362-370
27		Yu-Jen Huang, Jin-Fu Li: Testing Active Neighborhood Pattern-Sensitive Faults of Ternary Content Addressable Memories. European Test Symposium 2006: 55-62
26		Tsu-Wei Tseng, Jin-Fu Li, Chih-Chiang Hsu, Alex Pao, Kevin Chiu, Eliot Chen: A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs. ITC 2006: 1-9
	2005
25		Jin-Fu Li: Testing comparison faults of ternary CAMs based on comparison faults of binary CAMs. ASP-DAC 2005: 65-70
24		Jin-Fu Li, Tsu-Wei Tseng, Chin-Long Wey: An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories. DATE 2005: 574-579
23		Jin-Fu Li, Jiunn-Der Yu, Yu-Jen Huang: A design methodology for hybrid carry-lookahead/carry-select adders with reconfigurability. ISCAS (1) 2005: 77-80
22		Jin-Fu Li: Testing priority address encoder faults of content addressable memories. ITC 2005: 8
21		Jin-Fu Li, Chou-Kun Lin: Modeling and Testing Comparison Faults for Ternary Content Addressable Memories. VTS 2005: 60-65
20		Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu: A built-in self-repair design for RAMs with 2-D redundancy. IEEE Trans. VLSI Syst. 13(6): 742-745 (2005)
	2004
19		Jin-Fu Li, Chao-Da Huang: An Efficient Diagnosis Scheme for Random Access Memories. Asian Test Symposium 2004: 277-282
18		Jin-Fu Li, Chih-Chiang Hsu: Efficient Test Methodologies for Conditional Sum Adders. Asian Test Symposium 2004: 319-324
17		Jin-Fu Li: Diagnosing Binary Content Addressable Memories with Comparison and RAM Faults. IEICE Transactions 87-D(3): 601-608 (2004)
	2003
16		Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow: A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy. ITC 2003: 393-402
15		Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu Li: A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories. MTDT 2003: 53-
14		Chih-Tsun Huang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu: Built-in redundancy analysis for memory yield improvement. IEEE Transactions on Reliability 52(4): 386-399 (2003)
13		Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu: Testing and Diagnosis Methodologies for Embedded Content Addressable Memories. J. Electronic Testing 19(2): 207-215 (2003)
	2002
12		Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin: A Hierarchical Test Scheme for System-On-Chip Designs. DATE 2002: 486-490
11		Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu: A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories. IOLTW 2002: 262-
10		Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu: A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories. MTDT 2002: 68-
9		Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu: Testing and Diagnosing Embedded Content Addressable Memories. VTS 2002: 389-394
8		Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin: A Hierarchical Test Methodology for Systems on Chip. IEEE Micro 22(5): 69-81 (2002)
7		Jin-Fu Li, Cheng-Wen Wu: Efficient FFT network testing and diagnosis schemes. IEEE Trans. VLSI Syst. 10(3): 267-278 (2002)
6		Jin-Fu Li, Ruey-Shing Tzeng, Cheng-Wen Wu: Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test. J. Electronic Testing 18(4-5): 515-527 (2002)
5		Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin: A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM. J. Electronic Testing 18(6): 637-647 (2002)
	2001
4		Jin-Fu Li, Cheng-Wen Wu: Memory fault diagnosis by syndrome compression. DATE 2001: 97-101
3		Jin-Fu Li, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu: March-based RAM diagnosis algorithms for stuck-at and coupling faults. ITC 2001: 758-767
	2000
2		Chih-Wea Wang, Chi-Feng Wu, Jin-Fu Li, Cheng-Wen Wu, Tony Teng, Kevin Chiu, Hsiao-Ping Lin: A built-in self-test and self-diagnosis scheme for embedded SRAM. Asian Test Symposium 2000: 45-50
	1999
1		Jin-Fu Li, Cheng-Wen Wu: Testable and Fault Tolerant Design for FFT Networks. DFT 1999: 201-209

Coauthor Index

1	Da-Ming Chang	[28] [29] [40]
2	Eliot Chen	[26] [37]
3	Jeng-Bin Chen	[8] [12]
4	Ji-Jan Chen	[59] [64]
5	Shao-I Chen	[8] [12]
6	Ting-Ju Chen	[65]
7	Chuang Cheng	[8] [12]
8	Kuo-Liang Cheng	[3]
9	Kwang-Ting Cheng (Kwang-Ting (Tim) Cheng)	[39]
10	Chun-Chuan Chi	[57]
11	Kevin Chiu	[2] [5] [26] [37]
12	Che-Wei Chou	[56] [58] [59]
13	Yung-Fa Chou	[59] [64]
14	Eugene Chow	[16]
15	Li-Ming Denq	[15]
16	Chih-Sheng Hou	[50] [53] [54] [58] [62]
17	Archer Hsu	[16]
18	Chih-Chiang Hsu	[18] [26] [51]
19	Yong-Jyun Hu	[44] [48]
20	Bing-Wei Huang	[45]
21	Chao-Da Huang	[19] [31] [34]
22	Chih-Tsun Huang	[3] [14]
23	Hsin-Jung Huang	[8] [12]
24	Rei-Fu Huang	[10] [11] [15] [16] [20] [35]
25	Yu-Jen Huang	[23] [27] [28] [30] [37] [40] [43] [44] [47] [48] [49] [55] [56] [64]
26	Chi-Yi Hwang	[8] [12]
27	Ding-Ming Kwai	[59] [64]
28	Chou-Kun Lin	[21]
29	Hsiao-Ping Lin	[2] [5] [8] [12]
30	Hsiang-Ning Liu	[38] [43]
31	Hsing-Chen Lu	[46]
32	Shyue-Kung Lu	[66]
33	Alex Pao	[26] [37]
34	Hong-Ming Shieh	[41]
35	Chih-Pin Su	[8] [12]
36	Tony Teng	[2] [5]
37	Peir-Yuan Tsai	[16]
38	Tsu-Wei Tseng	[24] [26] [29] [34] [36] [37] [42] [49] [50] [51] [53] [54] [61] [62] [63] [65]
39	Ruey-Shing Tzeng	[6] [9] [13]
40	Chih-Wea Wang	[2] [5]
41	Chin-Long Wey	[24] [36] [38]
42	Cheng-Wen Wu	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [20] [35] [57] [59] [60] [64] [66]
43	Chi-Feng Wu	[2] [5] [14]
44	Chun-Hsien Wu	[37]
45	Yao-Xian Yang	[38]
46	Jen-Chieh Yeh	[10] [11] [16] [20] [35]
47	Yun-Chao You	[55]
48	Jiunn-Der Yu	[23]
49	Feijun (Frank) Zheng	[39]

Colors in the list of coauthors

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