Huawei Li

	2012
70		Xiang Fu, Huawei Li, Xiaowei Li: Testable Path Selection and Grouping for Faster Than At-Speed Testing. IEEE Trans. VLSI Syst. 20(2): 236-247 (2012)
	2011
69		Yuntan Fang, Huawei Li, Xiaowei Li: A Fault Criticality Evaluation Framework of Digital Systems for Error Tolerant Video Applications. Asian Test Symposium 2011: 329-334
68		Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li: Flex memory: Exploiting and managing abundant off-chip optical bandwidth. DATE 2011: 968-973
67		Binzhang Fu, Yinhe Han, Jun Ma, Huawei Li, Xiaowei Li: An abacus turn model for time/space-efficient reconfigurable routing. ISCA 2011: 259-270
66		Songwei Pei, Huawei Li, Xiaowei Li: A unified test architecture for on-line and off-line delay fault detections. VTS 2011: 272-277
65		Ying Zhang, Huawei Li, Yinghua Min, Xiaowei Li: Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects. IEEE Trans. VLSI Syst. 19(10): 1787-1800 (2011)
64		Minjin Zhang, Huawei Li, Xiaowei Li: Path Delay Test Generation Toward Activation of Worst Case Coupling Effects. IEEE Trans. VLSI Syst. 19(11): 1969-1982 (2011)
63		Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li: A New Multiple-Round Dimension-Order Routing for Networks-on-Chip. IEICE Transactions 94-D(4): 809-821 (2011)
62		Song Jin, Yinhe Han, Huawei Li, Xiaowei Li: Statistical lifetime reliability optimization considering joint effect of process variation and aging. Integration 44(3): 185-191 (2011)
	2010
61		Zijian He, Tao Lv, Huawei Li, Xiaowei Li: Graph partition based path selection for testing of small delay defects. ASP-DAC 2010: 499-504
60		Song Jin, Yinhe Han, Huawei Li, Xiaowei Li: P^(2)CLRAF: An Pre- and Post-Silicon Cooperated Circuit Lifetime Reliability Analysis Framework. Asian Test Symposium 2010: 117-120
59		Zijian He, Tao Lv, Huawei Li, Xiaowei Li: An Efficient Algorithm for Finding a Universal Set of Testable Long Paths. Asian Test Symposium 2010: 319-324
58		Ying Zhang, Huawei Li, Xiaowei Li: Software-Based Self-Testing of Processors Using Expanded Instructions. Asian Test Symposium 2010: 415-420
57		Xiang Fu, Huawei Li, Xiaowei Li: On Selection of Testable Paths with Specified Lengths for Faster-Than-At-Speed Testing. Asian Test Symposium 2010: 45-48
56		Minjie Jin, Huawei Li, Yanhua Xiong, Jie Gao: The Application of the Optimum of MDOD in Structure Design of Double Reels for Wrapped Hoist. CASoN 2010: 675-678
55		Songwei Pei, Huawei Li, Xiaowei Li: An on-chip clock generation scheme for faster-than-at-speed delay testing. DATE 2010: 1353-1356
54		Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li: Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs. DATE 2010: 933-936
53		Huawei Li, Dawen Xu, Yinhe Han, Kwang-Ting Cheng, Xiaowei Li: nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications. ITC 2010: 343-352
52		Zijian He, Tao Lv, Huawei Li, Xiaowei Li: On generation of a universal path candidate set containing testable long paths. ITC 2010: 816
51		Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li: Address Remapping for Static NUCA in NoC-Based Degradable Chip-Multiprocessors. PRDC 2010: 70-76
50		Zijian He, Tao Lv, Huawei Li, Xiaowei Li: Fast path selection for testing of small delay defects considering path correlations. VTS 2010: 3-8
49		Xiang Fu, Huawei Li, Xiaowei Li: Testable Critical Path Selection Considering Process Variation. IEICE Transactions 93-D(1): 59-67 (2010)
	2009
48		Songwei Pei, Huawei Li, Xiaowei Li: A Low Overhead On-Chip Path Delay Measurement Circuit. Asian Test Symposium 2009: 145-150
47		Zichu Qi, Hui Liu, Xiangku Li, Da Wang, Yinhe Han, Huawei Li, Weiwu Hu: A Scalable Scan Architecture for Godson-3 Multicore Microprocessor. Asian Test Symposium 2009: 219-224
46		Song Jin, Yinhe Han, Lei Zhang, Huawei Li, Xiaowei Li, Guihai Yan: M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay. Asian Test Symposium 2009: 437-442
45		Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li: A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes. PRDC 2009: 276-281
44		Jie Wang, Huawei Li, Yinghua Min, Xiaowei Li, Huaguo Liang: Impact of Hazards on Pattern Selection for Small Delay Defects. PRDC 2009: 49-54
43		Li Liu, Jishun Kuang, Huawei Li: Small Delay Fault Simulation for Sequential Circuits. PRDC 2009: 63-68
42		Songwei Pei, Huawei Li, Xiaowei Li: Flip-Flop Selection for Transition Test Pattern Reduction Using Partial Enhanced Scan. PRDC 2009: 75-80
41		Tao Lv, Huawei Li, Xiaowei Li: Automatic Selection of Internal Observation Signals for Design Verification. VTS 2009: 203-208
40		Lei Zhang, Yinhe Han, Qiang Xu, Xiaowei Li, Huawei Li: On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems. IEEE Trans. VLSI Syst. 17(9): 1173-1186 (2009)
39		Ying Zhang, Huawei Li, Xiaowei Li: Selected Crosstalk Avoidance Code for Reliable Network-on-Chip. J. Comput. Sci. Technol. 24(6): 1074-1085 (2009)
	2008
38		Fei Wang, Yu Hu, Huawei Li, Xiaowei Li: A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults. ASP-DAC 2008: 571-576
37		Xiang Fu, Huawei Li, Yu Hu, Xiaowei Li: Robust test generation for power supply noise induced path delay faults. ASP-DAC 2008: 659-662
36		Da Wang, Rui Li, Yu Hu, Huawei Li, Xiaowei Li: A Case Study on At-Speed Testing for a Gigahertz Microprocessor. DELTA 2008: 326-331
35		Minjin Zhang, Huawei Li, Xiaowei Li: Static Crosstalk Noise Analysis with Transition Map. DELTA 2008: 462-465
34		Hui Liu, Huawei Li, Yu Hu, Xiaowei Li: A Scan-Based Delay Test Method for Reduction of Overtesting. DELTA 2008: 521-526
33		Fei Wang, Yu Hu, Huawei Li, Xiaowei Li, Jing Ye, Yu Huang: Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects. ITC 2008: 1-10
32		Ying Zhang, Huawei Li, Xiaowei Li, Yu Hu: Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects. VTS 2008: 377-382
31		Minjin Zhang, Huawei Li, Xiaowei Li: Multiple Coupling Effects Oriented Path Delay Test Generation. VTS 2008: 383-388
30		Da Wang, Yu Hu, Huawei Li, Xiaowei Li: Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor. J. Comput. Sci. Technol. 23(6): 1037-1046 (2008)
	2007
29		Lei Zhang, Huawei Li, Xiaowei Li: A Routing Algorithm for Random Error Tolerance in Network-on-Chip. HCI (4) 2007: 1210-1219
28		Da Wang, Xiaoxin Fan, Xiang Fu, Hui Liu, Ke Wen, Rui Li, Huawei Li, Yu Hu, Xiaowei Li: The design-for-testability features of a general purpose microprocessor. ITC 2007: 1-9
27		Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra: Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit. IEEE Trans. VLSI Syst. 15(5): 531-540 (2007)
	2006
26		Huawei Li, Yu Fan, Tao Wu: Impact of Load Characteristics and Low-Voltage Load Shedding Schedule on Dynamic Voltage Stability. CCECE 2006: 2249-2252
25		Huawei Li, Yu Fan, Rong Shi: Chaos and Ferroresonance. CCECE 2006: 494-497
24		Tong Liu, Huawei Li, Xiaowei Li, Yinhe Han: Fast Packet Classification using Group Bit Vector. GLOBECOM 2006
23		Huawei Li, Pei-Fu Shen, Xiaowei Li: Robust Test Generation for Precise Crosstalk-induced Path Delay Faults. VTS 2006: 300-305
22		Yinhe Han, Xiaowei Li, Huawei Li, Anshuman Chandra: Embedded test resource for SoC to reduce required tester channels based on advanced convolutional codes. IEEE T. Instrumentation and Measurement 55(2): 389-399 (2006)
21		Yu Hu, Yinhe Han, Xiaowei Li, Huawei Li, Xiaoqing Wen: Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time. IEICE Transactions 89-D(10): 2616-2625 (2006)
20		Yinhe Han, Huawei Li, Xiaowei Li, Anshuman Chandra: Response compaction for system-on-a-chip based on advanced convolutional codes. Science in China Series F: Information Sciences 49(2): 262-272 (2006)
	2005
19		Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li: Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code. ASP-DAC 2005: 53-58
18		Shuguang Gong, Huawei Li, Yufeng Xu, Tong Liu, Xiaowei Li: Design of an efficient memory subsystem for network processor. ASP-DAC 2005: 897-900
17		Pei-Fu Shen, Huawei Li, Yongjun Xu, Xiaowei Li: Non-robust Test Generation for Crosstalk-Induced Delay Faults. Asian Test Symposium 2005: 120-125
16		Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li: Using MUXs Network to Hide Bunches of Scan Chains. ISQED 2005: 238-243
15		Yu Hu, Xiaowei Li, Huawei Li, Xiaoqing Wen: Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time. PRDC 2005: 175-182
14		Yinhe Han, Yu Hu, Xiaowei Li, Huawei Li, Anshuman Chandra, Xiaoqing Wen: Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores. IEICE Transactions 88-D(9): 2126-2134 (2005)
13		Yinhe Han, Xiaowei Li, Huawei Li, Anshuman Chandra: Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction. J. Comput. Sci. Technol. 20(2): 201-209 (2005)
12		Huawei Li, Xiaowei Li: Selection of Crosstalk-Induced Faults in Enhanced Delay Test. J. Electronic Testing 21(2): 181-195 (2005)
	2004
11		Yu Hu, Yinhe Han, Huawei Li, Tao Lv, Xiaowei Li: Pair Balance-Based Test Scheduling for SOCs. Asian Test Symposium 2004: 236-241
10		Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra: Rapid and Energy-Efficient Testing for Embedded Cores. Asian Test Symposium 2004: 8-13
9		Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra: Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes. DFT 2004: 298-305
	2003
8		Huawei Li, Yue Zhang, Xiaowei Li: Delay Test Pattern Generation Considering Crosstalk-Induced Effects. Asian Test Symposium 2003: 178-183
7		Yinhe Han, Yongjun Xu, Huawei Li, Xiaowei Li, Anshuman Chandra: Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste. Asian Test Symposium 2003: 440-445
6		Zhigang Yin, Yinghua Min, Xiaowei Li, Huawei Li: A Novel RT-Level Behavioral Description Based ATPG Method. J. Comput. Sci. Technol. 18(3): 308-317 (2003)
	2002
5		Zuying Luo, Xiaowei Li, Huawei Li, Shiyuan Yang, Yinghua Min: Test Power Optimization Techniques for CMOS Circuits. Asian Test Symposium 2002: 332-337
	2001
4		Huawei Li, Yinghua Min, Zhongcheng Li: An RT-Level ATPG Based on Clustering of Circuit States. Asian Test Symposium 2001: 213-218
3		Xiaowei Li, Huawei Li, Yinghua Min: Reducing Power Dissipation during At-Speed Test Application. DFT 2001: 116-
	2000
2		Huawei Li, Zhongcheng Li, Yinghua Min: Reduction of Number of Paths to be Tested in Delay Testing. J. Electronic Testing 16(5): 477-485 (2000)
	1998
1		Huawei Li, Zhongcheng Li, Yinghua Min: Delay Testing with Double Observations. Asian Test Symposium 1998: 96-

Coauthor Index

1	Anshuman Chandra	[7] [9] [10] [13] [14] [20] [22] [27]
2	Kwang-Ting Cheng (Kwang-Ting (Tim) Cheng)	[53]
3	Xiaoxin Fan	[28]
4	Yu Fan	[25] [26]
5	Yuntan Fang	[69]
6	Binzhang Fu	[45] [54] [63] [67]
7	Xiang Fu	[28] [37] [49] [57] [70]
8	Jie Gao	[56]
9	Shuguang Gong	[18]
10	Yinhe Han	[7] [9] [10] [11] [13] [14] [16] [19] [20] [21] [22] [24] [27] [40] [45] [46] [47] [51] [53] [54] [60] [62] [63] [67] [68]
11	Zijian He	[50] [52] [59] [61]
12	Weiwu Hu	[47]
13	Yu Hu	[9] [10] [11] [14] [15] [16] [19] [21] [27] [28] [30] [32] [33] [34] [36] [37] [38]
14	Yu Huang	[33]
15	Minjie Jin	[56]
16	Song Jin	[46] [60] [62]
17	Jishun Kuang	[43]
18	Rui Li	[28] [36]
19	Xiangku Li	[47]
20	Xiaowei Li	[3] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [27] [28] [29] [30] [31] [32] [33] [34] [35] [36] [37] [38] [39] [40] [41] [42] [44] [45] [46] [48] [49] [50] [51] [52] [53] [54] [55] [57] [58] [59] [60] [61] [62] [63] [64] [65] [66] [67] [68] [69] [70]
21	Zhongcheng Li	[1] [2] [4]
22	Huaguo Liang	[44]
23	Hui Liu	[28] [34] [47]
24	Li Liu	[43]
25	Tong Liu	[18] [24]
26	Zuying Luo	[5]
27	Tao Lv	[11] [41] [50] [52] [59] [61]
28	Jun Ma	[67]
29	Yinghua Min	[1] [2] [3] [4] [5] [6] [44] [65]
30	Songwei Pei	[42] [48] [55] [66]
31	Zichu Qi	[47]
32	Pei-Fu Shen	[17] [23]
33	Rong Shi	[25]
34	Da Wang	[28] [30] [36] [47]
35	Fei Wang	[33] [38]
36	Jie Wang	[44]
37	Ying Wang	[51] [68]
38	Ke Wen	[28]
39	Xiaoqing Wen	[14] [15] [21]
40	Tao Wu	[26]
41	Yanhua Xiong	[56]
42	Dawen Xu	[53]
43	Qiang Xu	[40]
44	Yongjun Xu	[7] [17]
45	Yufeng Xu	[18]
46	Guihai Yan	[46]
47	Shiyuan Yang	[5]
48	Jing Ye	[33]
49	Zhigang Yin	[6]
50	Minjin Zhang	[31] [35] [64]
51	Ying Zhang	[32] [39] [58] [65]
52	Yue Zhang	[8]
53	Lei Zhang	[29] [40] [46] [51] [68]

Colors in the list of coauthors

Last update Sun Jun 3 16:06:10 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page