Régis Leveugle

	2011
76		Paolo Maistri, Régis Leveugle: 10-Gigabit Throughput and Low Area for a Hardware Implementation of the Advanced Encryption Standard. DSD 2011: 266-269
75		Renaud Clavel, Laurence Pierre, Régis Leveugle: Towards Robustness Analysis Using PVS. ITP 2011: 71-86
74		Gaetan Canivet, Paolo Maistri, Régis Leveugle, Jessy Clédière, Florent Valette, Marc Renaudin: Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA. J. Cryptology 24(2): 247-268 (2011)
	2010
73		Gaetan Canivet, Paolo Maistri, Régis Leveugle, Frédéric Valette, Jessy Clédière, Marc Renaudin: Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGA. ASAP 2010: 115-122
72		Gaetan Canivet, P. Maistn, Régis Leveugle, Frédéric Valette, Jessy Clédière, Marc Renaudin: Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA. European Test Symposium 2010: 251
71		Régis Leveugle: Early Robustness Evaluation of Digital Integrated Systems. FDL 2010: 69-70
70		Régis Leveugle, Mohamed Ben Jrad: A new methodology for accurate predictive robustness analysis of designs implemented in SRAM-based FPGAs. ICECS 2010: 1172-1175
	2009
69		Régis Leveugle, A. Calvez, Paolo Maistri, Pierre Vanhauwaert: Statistical fault injection: Quantified error and confidence. DATE 2009: 502-506
68		Souheib Baarir, Cécile Braunstein, Renaud Clavel, Emmanuelle Encrenaz, Jean-Michel Ilié, Régis Leveugle, Isabelle Mounier, Laurence Pierre, Denis Poitrenaud: Complementary Formal Approaches for Dependability Analysis. DFT 2009: 331-339
67		Paolo Maistri, Régis Leveugle: Towards automated fault pruning with Petri Nets. IOLTS 2009: 41-46
66		Gaetan Canivet, Régis Leveugle, Jessy Clédière, Frédéric Valette, Marc Renaudin: Characterization of Effective Laser Spots during Attacks in the Configuration of a Virtex-II FPGA. VTS 2009: 327-332
	2008
65		Gaetan Canivet, Jessy Clédière, Jean Baptiste Ferron, Frédéric Valette, Marc Renaudin, Régis Leveugle: Detailed Analyses of Single Laser Shot Effects in the Configuration of a Virtex-II FPGA. IOLTS 2008: 289-294
64		Paolo Maistri, Cyril Excoffon, Régis Leveugle: Software Self-Testing of a Symmetric Cipher with Error Detection Capability. IOLTS 2008: 79-84
63		Paolo Maistri, Régis Leveugle: Double-Data-Rate Computation as a Countermeasure against Fault Analysis. IEEE Trans. Computers 57(11): 1528-1539 (2008)
	2007
62		Régis Leveugle, Abdelaziz Ammari, V. Maingot, E. Teyssou, Pascal Moitrel, Christophe Mourtel, Nathalie Feyt, Jean-Baptiste Rigaud, Assia Tria: Experimental evaluation of protections against laser-induced faults and consequences on fault modeling. DATE 2007: 1587-1592
61		Michele Portolan, Régis Leveugle: Effective Checkpoint and Rollback Using Hardware/OS Collaboration. DFT 2007: 370-378
60		Paolo Maistri, Pierre Vanhauwaert, Régis Leveugle: Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault Injections. DFT 2007: 499-507
59		Paolo Maistri, Pierre Vanhauwaert, Régis Leveugle: A Novel Double-Data-Rate AES Architecture Resistant against Fault Injection. FDTC 2007: 54-61
58		Yannick Monnet, Marc Renaudin, Régis Leveugle: Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs. IOLTS 2007: 113-120
57		Régis Leveugle: Early Analysis of Fault-based Attack Effects in Secure Circuits. IEEE Trans. Computers 56(10): 1431-1434 (2007)
56		V. Maingot, Jean Baptiste Ferron, Régis Leveugle, Vincent Pouget, Alexandre Douin: Configuration errors analysis in SRAM-based FPGAs: Software tool and practical results. Microelectronics Reliability 47(9-11): 1836-1840 (2007)
	2006
55		Régis Leveugle, V. Maingot: On the Use of Information Redundancy When Designing Secure Chips. DDECS 2006: 141-142
54		Pierre Vanhauwaert, Régis Leveugle, Philippe Roche: A Flexible SoPC-based Fault Injection Environment. DDECS 2006: 192-197
53		Abdelaziz Ammari, Régis Leveugle, B. Nicolescu, Yvon Savaria: Evaluation of a Software-Based Error Detection Technique by RT-Level Fault Injection. DELTA 2006: 488-493
52		Yannick Monnet, Marc Renaudin, Régis Leveugle, Christophe Clavier, Pascal Moitrel: Case Study of a Fault Attack on Asynchronous DES Crypto-Processors. FDTC 2006: 88-97
51		Yannick Monnet, Marc Renaudin, Régis Leveugle, Nathalie Feyt, Pascal Moitrel, F. M'Buwa Nzenguet: Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor. IOLTS 2006: 125-130
50		Pierre Vanhauwaert, Régis Leveugle, Philippe Roche: Reduced Instrumentation and Optimized Fault Injection Control for Dependability Analysis. VLSI-SoC 2006: 391-396
49		Yannick Monnet, Marc Renaudin, Régis Leveugle: Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic. IEEE Trans. Computers 55(9): 1104-1115 (2006)
	2005
48		Yannick Monnet, Marc Renaudin, Régis Leveugle: Asynchronous circuits transient faults sensitivity evaluation. DAC 2005: 863-868
47		Michele Portolan, Régis Leveugle: Towards a Secure and Reliable System. EUC 2005: 1085-1098
46		Régis Leveugle: Introduction to the Special Session on Secure Implementations. IOLTS 2005: 115
45		Yannick Monnet, Marc Renaudin, Régis Leveugle: Hardening Techniques against Transient Faults for Asynchronous Circuits. IOLTS 2005: 129-134
44		Régis Leveugle, Yervant Zorian, Luca Breveglieri, André K. Nieuwland, Klaus Rothbart, Jean-Pierre Seifert: On-Line Testing for Secure Implementations: Design and Validation. IOLTS 2005: 211
43		Michele Portolan, Régis Leveugle: On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors. IOLTS 2005: 247-252
42		Régis Leveugle: A New Approach for Early Dependability Evaluation Based on Formal Property Checking and Controlled Mutations. IOLTS 2005: 260-265
41		Lorena Anghel, Régis Leveugle, Pierre Vanhauwaert: Evaluation of SET and SEU Effects at Multiple Abstraction Levels. IOLTS 2005: 309-312
40		Abdelaziz Ammari, K. Hadjiat, Régis Leveugle: Combined Fault Classification and Error Propagation Analysis to Refine RT-Level Dependability Evaluation. J. Electronic Testing 21(4): 365-376 (2005)
	2004
39		Régis Leveugle, Abdelaziz Ammari: Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow. DATE 2004: 590-595
38		Régis Leveugle, D. Cimonnet, Abdelaziz Ammari: System-Level Dependability Analysis with RT-Level Fault Injection Accuracy. DFT 2004: 451-458
37		Yannick Monnet, Marc Renaudin, Régis Leveugle: Asynchronous Circuits Sensitivity to Fault Injection. IOLTS 2004: 121-128
36		Michele Portolan, Régis Leveugle: Operating System Function Reuse to Achieve Low-Cost Fault Tolerance. IOLTS 2004: 167-174
35		Abdelaziz Ammari, K. Hadjiat, Régis Leveugle: On Combining Fault Classification and Error Propagation Analysis in RT-Level Dependability Evaluation. IOLTS 2004: 227-232
	2003
34		Abdelaziz Ammari, Régis Leveugle, Matteo Sonza Reorda, Massimo Violante: Detailed Comparison of Dependability Analyses Performed at RT and Gate Levels. DFT 2003: 336-343
33		Régis Leveugle, Lörinc Antoni, Béla Fehér: Dependability Analysis: A New Application for Run-Time Reconfiguration. IPDPS 2003: 173
32		Lörinc Antoni, Régis Leveugle, Béla Fehér: Using run-time reconfiguration for fault injection applications. IEEE T. Instrumentation and Measurement 52(5): 1468-1473 (2003)
31		Régis Leveugle, K. Hadjiat: Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments. J. Electronic Testing 19(5): 559-575 (2003)
30		Régis Leveugle, Glenn H. Chapman: Special section on defect and fault tolerance in VLSI systems. Microelectronics Journal 34(1): 1 (2003)
	2002
29		Régis Leveugle: Automatic Modifications of High Level VHDL Descriptions for Fault Detection or Tolerance. DATE 2002: 837-841
28		Lörinc Antoni, Régis Leveugle, Béla Fehér: Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes. DFT 2002: 245-253
27		Régis Leveugle, K. Hadjiat: Multi-Level Fault Injection Experiments Based on VHDL Descriptions: A Case Study. IOLTW 2002: 107-111
	2001
26		Régis Leveugle: A Low-Cost Hardware Approach to Dependability Validation of Ips. DFT 2001: 242-249
25		Raoul Velazco, Régis Leveugle, O. Calvo: Upset-Like Fault Injection in VHDL Descriptions: A Method and Preliminary Results. DFT 2001: 259-
24		Régis Leveugle, R. Cercueil: High Level Modifications of VHDL Descriptions for On-Line Test or Fault Tolerance. DFT 2001: 84-
	2000
23		Lörinc Antoni, Régis Leveugle, Béla Fehér: Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes. DFT 2000: 405-413
22		Régis Leveugle: Fault Injection in VHDL Descriptions and Emulation. DFT 2000: 414-
	1999
21		Alejandro Chagoya, Régis Leveugle: Experiments on Multimedia Support of VLSI Design teaching in the MODEM Project. MSE 1999: 82-83
	1997
20		X. Wendling, H. Chauvet, Lionel Revéret, R. Rochet, Régis Leveugle: Automatic and Optimized Synthesis of Dataparts with Fault Detection or Tolerance Capabilities. DFT 1997: 195-203
	1996
19		X. Wendling, R. Rochet, Régis Leveugle: Standard and ROM-based synthesis of FSMs with control flow checking capabilities. VTS 1996: 81-86
	1994
18		Régis Leveugle, R. Rochet, Gabriele Saucier: Alternative Approaches to Fault Detection in FSMs. DFT 1994: 271-279
17		T. Michel, Régis Leveugle, Gabriele Saucier, R. Doucet, P. Chapier: Taking Advantage of ASICs to Improve Dependability with Very Low Overheads. EDAC-ETC-EUROASIC 1994: 14-18
16		C. Safinia, Régis Leveugle, Gabriele Saucier: Taking Advantage of High Level Functional Information to Refine Timing Analysis and Timing Modeling. EDAC-ETC-EUROASIC 1994: 349-353
15		Régis Leveugle, Zahava Koren, Israel Koren, Gabriele Saucier, Norbert Wehn: The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis. IEEE Trans. Computers 43(12): 1398-1406 (1994)
	1993
14		Régis Leveugle: Optimized State Assignment of single fault Tolerant FSMs Based on SEC Codes. DAC 1993: 14-18
13		R. Rochet, Régis Leveugle, Gabriele Saucier: Analysis and Comparison of Fault Tolerant FSM Architectures Based on SEC Codes. DFT 1993: 9-16
12		Régis Leveugle, R. Rochet, Gabriele Saucier, L. Martinez, C. Pitot: A Synthesis Tool for Fault-Tolerant Finite State Machines. FTCS 1993: 502-511
11		Régis Leveugle, X. Delord, Gabriele Saucier: Influence of Error Correlations on the Signature Analysis Aliasing. ICCD 1993: 584-587
10		Régis Leveugle: Test of single fault tolerant controllers in VLSI circuits. VLSI 1993: 123-132
	1992
9		Régis Leveugle, C. Safina: Generation of optimized datapaths: bit-slice versus standard cells. Synthesis for Control Dominated Circuits 1992: 153-166
8		C. Safina, Régis Leveugle: Clocking scheme selection for circuits made up of a controller and a datapath. Synthesis for Control Dominated Circuits 1992: 293-308
7		Pierre Abouzeid, Régis Leveugle, Gabriele Saucier: Logic Synthesis for Automatic Layout. Synthesis for Control Dominated Circuits 1992: 335-343
6		L. Gerbaux, Régis Leveugle, Gabriele Saucier: Synthesis of large controllers using ROM or PLA generators. Synthesis for Control Dominated Circuits 1992: 47-59
	1991
5		T. Michel, Régis Leveugle, Gabriele Saucier: A New Approach to Control Flow Checking Without Program Modification. FTCS 1991: 334-343
4		Margot Karam, Régis Leveugle, Gabriele Saucier: Hierarchical Test Generation Based on Delayed Propagation. ITC 1991: 739-747
	1990
3		Régis Leveugle, T. Michel, Gabriele Saucier: Design of microprocessors with built-in on-line test. FTCS 1990: 450-456
2		Régis Leveugle, Gabriele Saucier: Optimized Synthesis of Concurrently Checked Controllers. IEEE Trans. Computers 39(4): 419-425 (1990)
	1989
1		Régis Leveugle, Gabriele Saucier: Optimized Synthesis of Dedicated Controllers with Concurrent Checking Capabilities. ITC 1989: 355-363

Coauthor Index

1	Pierre Abouzeid	[7]
2	Abdelaziz Ammari	[34] [35] [38] [39] [40] [53] [62]
3	Lorena Anghel	[41]
4	Lörinc Antoni	[23] [28] [32] [33]
5	Souheib Baarir	[68]
6	Cécile Braunstein	[68]
7	Luca Breveglieri	[44]
8	A. Calvez	[69]
9	O. Calvo	[25]
10	Gaetan Canivet	[65] [66] [72] [73] [74]
11	R. Cercueil	[24]
12	Alejandro Chagoya	[21]
13	P. Chapier	[17]
14	Glenn H. Chapman	[30]
15	H. Chauvet	[20]
16	D. Cimonnet	[38]
17	Renaud Clavel	[68] [75]
18	Christophe Clavier	[52]
19	Jessy Clédière	[65] [66] [72] [73] [74]
20	X. Delord	[11]
21	R. Doucet	[17]
22	Alexandre Douin	[56]
23	Emmanuelle Encrenaz-Tiphène (Emmanuelle Encrenaz)	[68]
24	Cyril Excoffon	[64]
25	Béla Fehér	[23] [28] [32] [33]
26	Jean Baptiste Ferron	[56] [65]
27	Nathalie Feyt	[51] [62]
28	L. Gerbaux	[6]
29	K. Hadjiat	[27] [31] [35] [40]
30	Jean-Michel Ilié (Jean Michel Ilié)	[68]
31	Mohamed Ben Jrad	[70]
32	Margot Karam	[4]
33	Israel Koren	[15]
34	Zahava Koren	[15]
35	V. Maingot	[55] [56] [62]
36	P. Maistn	[72]
37	Paolo Maistri	[59] [60] [63] [64] [67] [69] [73] [74] [76]
38	L. Martinez	[12]
39	T. Michel	[3] [5] [17]
40	Pascal Moitrel	[51] [52] [62]
41	Yannick Monnet	[37] [45] [48] [49] [51] [52] [58]
42	Isabelle Mounier	[68]
43	Christophe Mourtel	[62]
44	B. Nicolescu	[53]
45	André K. Nieuwland	[44]
46	F. M'Buwa Nzenguet	[51]
47	Laurence Pierre (Laurence V. Pierre)	[68] [75]
48	C. Pitot	[12]
49	Denis Poitrenaud	[68]
50	Michele Portolan	[36] [43] [47] [61]
51	Vincent Pouget	[56]
52	Marc Renaudin	[37] [45] [48] [49] [51] [52] [58] [65] [66] [72] [73] [74]
53	Matteo Sonza Reorda	[34]
54	Lionel Revéret	[20]
55	Jean-Baptiste Rigaud	[62]
56	Philippe Roche	[50] [54]
57	R. Rochet	[12] [13] [18] [19] [20]
58	Klaus Rothbart	[44]
59	C. Safina	[8] [9]
60	C. Safinia	[16]
61	Gabriele Saucier	[1] [2] [3] [4] [5] [6] [7] [11] [12] [13] [15] [16] [17] [18]
62	Yvon Savaria	[53]
63	Jean-Pierre Seifert	[44]
64	E. Teyssou	[62]
65	Assia Tria	[62]
66	Florent Valette	[74]
67	Frédéric Valette	[65] [66] [72] [73]
68	Pierre Vanhauwaert	[41] [50] [54] [59] [60] [69]
69	Raoul Velazco	[25]
70	Massimo Violante	[34]
71	Norbert Wehn	[15]
72	X. Wendling	[19] [20]
73	Yervant Zorian	[44]

Colors in the list of coauthors

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