Guy Lemieux

Guy G. Lemieux, Guy G. F. Lemieux

University of British Columbia

	2012
41		Zhiduo Liu, Aaron Severance, Satnam Singh, Guy G. F. Lemieux: Accelerator compiler for the VENICE vector processor. FPGA 2012: 229-232
40		Yehdhih Ould Mohammed Moctar, Nithin George, Hadi Parandeh-Afshar, Paolo Ienne, Guy G. F. Lemieux, Philip Brisk: Reducing the cost of floating-point mantissa alignment and normalization in FPGAs. FPGA 2012: 255-264
39		Chris C. Wang, Guy G. F. Lemieux: Parallel FPGA placement based on individual LUT placement (abstract only). FPGA 2012: 269
38		David Grant, Graeme Smecher, Guy G. F. Lemieux, Rosemary Francis: Rapid Synthesis and Simulation of Computational Circuits in an MPPA. Signal Processing Systems 67(1): 47-63 (2012)
	2011
37		Jonathan Rose, Guy G. Lemieux: The role of FPGAs in a converged future with heterogeneous programmable processors: pre-conference workshop. FPGA 2011: 1-2
36		David Grant, Chris Wang, Guy G. Lemieux: A CAD framework for Malibu: an FPGA with time-multiplexed coarse-grained elements. FPGA 2011: 123-132
35		Christopher Han-Yu Chou, Aaron Severance, Alex D. Brant, Zhiduo Liu, Saurabh Sant, Guy G. Lemieux: VEGAS: soft vector processor with scratchpad memory. FPGA 2011: 15-24
34		Chris C. Wang, Guy G. Lemieux: Scalable and deterministic timing-driven parallel placement for FPGAs. FPGA 2011: 153-162
33		Ameer Abdelhadi, Guy G. F. Lemieux: Configuration Bitstream Reduction for SRAM-based FPGAs by Enumerating LUT Input Permutations. ReConFig 2011: 20-26
32		Jeffrey B. Goeders, Guy G. F. Lemieux, Steven J. E. Wilton: Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition. ReConFig 2011: 41-48
31		Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton: Performance and Cost Tradeoffs in Metal-Programmable Structured ASICs (MPSAs). IEEE Trans. VLSI Syst. 19(12): 2195-2208 (2011)
	2010
30		Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton: The impact of interconnect architecture on via-programmed structured ASICs (VPSAs). FPGA 2010: 263-272
29		Mehdi Alimadadi, Samad Sheikhaei, Guy Lemieux, Shahriar Mirabbasi, William Dunford, Patrick Palmer: A 4 GHz Non-Resonant Clock Driver With Inductor-Assisted Energy Return to Power Grid. IEEE Trans. on Circuits and Systems 57-I(8): 2099-2108 (2010)
	2009
28		Johnny Tsung Lin Ho, Guy G. Lemieux: PERG-Rx: a hardware pattern-matching engine supporting limited regular expressions. FPGA 2009: 257-260
27		Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet: Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs. FPGA 2009: 43-52
26		David Leong, Guy G. Lemieux: Replace: An incremental placement algorithm for field programmable gate arrays. FPL 2009: 154-161
25		Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet: Estimating reliability and throughput of source-synchronous wave-pipelined interconnect. NOCS 2009: 234-243
24		Jason Yu, Christopher Eagleston, Christopher Han-Yu Chou, Maxime Perreault, Guy G. Lemieux: Vector Processing as a Soft Processor Accelerator. TRETS 2(2): (2009)
	2008
23		Guy G. Lemieux, Tarek A. El-Ghazawi: Designing with extreme parallelism. FPGA 2008: 1-2
22		Tarek A. El-Ghazawi, Guy G. Lemieux: Extreme parallel architectures for the masses. FPGA 2008: 127-128
21		Jason Yu, Guy G. Lemieux, Christopher Eagleston: Vector processing as a soft-core CPU accelerator. FPGA 2008: 222-232
20		Mehdi Alimadadi, Samad Sheikhaei, Guy Lemieux, Shahriar Mirabbasi, William Dunford, Patrick Palmer: Energy Recovery from High-Frequency Clocks Using DC-DC Converters. ISVLSI 2008: 162-167
19		Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton: GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering. IEEE Trans. VLSI Syst. 16(11): 1521-1534 (2008)
18		Edmund Lee, Guy Lemieux, Shahriar Mirabbasi: Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays. Signal Processing Systems 51(1): 57-76 (2008)
17		David Grant, Guy G. Lemieux: Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing. TRETS 1(3): (2008)
	2007
16		Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton: GlitchLess: an active glitch minimization technique for FPGAs. FPGA 2007: 156-165
15		David Yeager, Darius Chiu, Guy G. Lemieux: Congestion estimation and localization in FPGAS: a visual tool for interconnect prediction. SLIP 2007: 33-40
14		Paul Teehan, Mark R. Greenstreet, Guy G. Lemieux: A Survey and Taxonomy of GALS Design Styles. IEEE Design & Test of Computers 24(5): 418-428 (2007)
	2006
13		David Grant, Scott Chin, Guy G. Lemieux: Semi-Synthetic Circuit Generation Using Graph Monomorphism for Testing Incremental Placement and Incremental Routing Tools. FPL 2006: 1-4
12		Marvin Tom, David Leong, Guy G. Lemieux: Un/DoPack: re-clustering of large system-on-chip designs with interconnect variation for low-cost FPGAs. ICCAD 2006: 680-687
	2005
11		Marvin Tom, Guy G. Lemieux: Logic block clustering of large designs for channel-width constrained FPGAs. DAC 2005: 726-731
10		Anthony J. Yu, Guy G. Lemieux: Defect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield Enhancement. FPL 2005: 255-262
9		Anthony J. Yu, Guy G. Lemieux: FPGA Defect Tolerance: Impact of Granularity. FPT 2005: 189-196
	2004
8		Guy Lemieux, David A. Lewis: Design of interconnection networks for programmable logic. Kluwer 2004: I-XX, 1-206
	2002
7		Guy G. Lemieux, David M. Lewis: Circuit design of routing switches. FPGA 2002: 19-28
6		Guy G. Lemieux, David M. Lewis: Analytical Framework for Switch Block Design. FPL 2002: 122-131
	2001
5		Guy G. Lemieux, David M. Lewis: Using sparse crossbars within LUT. FPGA 2001: 59-68
	2000
4		Guy G. Lemieux, Paul Leventis, David M. Lewis: Generating highly-routable sparse crossbars for PLDs. FPGA 2000: 155-164
3		R. Grindley, Tarek S. Abdelrahman, Stephen Dean Brown, S. Caranci, D. DeVries, Benjamin Gamsa, A. Grbic, M. Gusat, R. Ho, Orran Krieger, Guy G. Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic: The NUMAchine Multiprocessor. ICPP 2000: 487-496
	1998
2		A. Grbic, Stephen Dean Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic: Design and Implementation of the NUMAchine Multiprocessor. DAC 1998: 66-69
	1997
1		Guy G. Lemieux, Stephen Dean Brown, Daniel Vranesic: On two-step routing for FPGAS. ISPD 1997: 60-66

Coauthor Index

1	Ameer Abdelhadi	[33]
2	Tarek S. Abdelrahman	[3]
3	Usman Ahmed	[30] [31]
4	Mehdi Alimadadi	[20] [29]
5	Alex D. Brant	[35]
6	Philip Brisk	[40]
7	Stephen Dean Brown	[1] [2] [3]
8	S. Caranci	[2] [3]
9	Scott Chin	[13]
10	Darius Chiu	[15]
11	Christopher Han-Yu Chou	[24] [35]
12	D. DeVries	[3]
13	William Dunford	[20] [29]
14	Christopher Eagleston	[21] [24]
15	Tarek A. El-Ghazawi	[22] [23]
16	Rosemary Francis	[38]
17	Benjamin Gamsa	[3]
18	Nithin George	[40]
19	Jeffrey B. Goeders	[32]
20	David Grant	[13] [17] [36] [38]
21	A. Grbic	[2] [3]
22	Mark R. Greenstreet	[14] [25] [27]
23	R. Grindley	[2] [3]
24	M. Gusat	[2] [3]
25	Johnny Tsung Lin Ho	[28]
26	R. Ho	[3]
27	Paolo Ienne	[40]
28	Orran Krieger	[3]
29	Julien Lamoureux	[16] [19]
30	Edmund Lee	[18]
31	David Leong	[12] [26]
32	Paul Leventis	[4]
33	David A. Lewis	[8]
34	David M. Lewis	[4] [5] [6] [7]
35	Zhiduo Liu	[35] [41]
36	K. Loveless	[2] [3]
37	Naraig Manjikian	[2] [3]
38	P. McHardy	[3]
39	Shahriar Mirabbasi	[18] [20] [29]
40	Yehdhih Ould Mohammed Moctar	[40]
41	Patrick Palmer	[20] [29]
42	Hadi Parandeh-Afshar	[40]
43	Maxime Perreault	[24]
44	Jonathan Rose	[37]
45	Saurabh Sant	[35]
46	Aaron Severance	[35] [41]
47	Samad Sheikhaei	[20] [29]
48	Satnam Singh	[41]
49	Graeme Smecher	[38]
50	Sinisa Srbljic	[2] [3]
51	Michael Stumm	[2] [3]
52	Paul Teehan	[14] [25] [27]
53	Marvin Tom	[11] [12]
54	Daniel Vranesic	[1]
55	Zvonko G. Vranesic	[2] [3]
56	Chris Wang	[36]
57	Chris C. Wang	[34] [39]
58	Steven J. E. Wilton	[16] [19] [30] [31] [32]
59	David Yeager	[15]
60	Anthony J. Yu	[9] [10]
61	Jason Yu	[21] [24]
62	Zeljko Zilic	[2] [3]

Colors in the list of coauthors

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