 | 2010 |
|---|
| 8 |       | Igor Lemberski,
Petr Fiser:
Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Constraints.
DSD 2010: 155-162 |
| 2009 |
|---|
| 7 | | Igor Lemberski,
Petr Fiser:
Asynchronous two-level logic of reduced cost.
DDECS 2009: 68-73 |
| 2007 |
|---|
| 6 |  | Igor Lemberski:
Cost Effective Implementation of Asynchronous Two-Level Logic.
World Congress on Engineering 2007: 159-164 |
| 5 | | Igor Lemberski:
Avoiding Hazards for Speed-Independent Logic Design.
World Congress on Engineering 2007: 274-278 |
| 2002 |
|---|
| 4 | | Igor Lemberski,
Mark B. Josephs:
Optimal Two-Level Delay - Insensitive Implementation of Logic Functions.
PATMOS 2002: 92-100 |
| 1999 |
|---|
| 3 | | Igor Lemberski:
Methodology of Logic Synthesis for Implementation Using Heterogeneous LUT FPGAs.
Great Lakes Symposium on VLSI 1999: 242-243 |
| 1998 |
|---|
| 2 | | Igor Lemberski:
Modified Approach to Automata State Encoding for LUT FPGA Implementation.
EUROMICRO 1998: 10196-10199 |
| 1 | | Igor Lemberski,
M. Ratniece:
XILINX4000 Architecture-Driven Synthesis for Speed.
FPL 1998: 476-480 |
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