Yuanwu Lei

	2012
14		Rongchun Li, Yong Dou, Yuanwu Lei, Shi-Ce Ni, Song Guo: Design and Implementation of the Parameterized Multi-Standard High-Throughput Radix-4 Viterbi Decoder on FPGA. IEICE Transactions 95-B(5): 1602-1611 (2012)
	2011
13		Yuanwu Lei, Yong Dou, Song Guo, Jie Zhou: FPGA Implementation of Variable-Precision Floating-Point Arithmetic. APPT 2011: 127-141
12		Yuanwu Lei, Yong Dou, Jie Zhou, Sufeng Wang: VPFPAP: A Special-Purpose VLIW Processor for Variable-Precision Floating-Point Arithmetic. FPL 2011: 252-257
11		Yuanwu Lei, Yong Dou, Li Shen, Jie Zhou, Song Guo: Special-purposed VLIW architecture for IEEE-754 quadruple precision elementary functions on FPGA. ICCD 2011: 219-225
10		Yuanwu Lei, Yong Dou, Jie Zhou: FPGA-Specific Custom VLIW Architecture for Arbitrary Precision Floating-Point Arithmetic. IEICE Transactions 94-D(11): 2173-2183 (2011)
	2010
9		Yong Dou, Yuanwu Lei, Guiming Wu, Song Guo, Jie Zhou, Li Shen: FPGA accelerating double/quad-double high precision floating-point applications for ExaScale computing. ICS 2010: 325-336
8		Yong Dou, Jie Zhou, Guiming Wu, Jingfei Jiang, Yuanwu Lei, Shi-Ce Ni: A Unified Co-Processor Architecture for Matrix Decomposition. J. Comput. Sci. Technol. 25(4): 874-885 (2010)
	2009
7		Jie Zhou, Yong Dou, Jianxun Zhao, Fei Xia, Yuanwu Lei, Yuxing Tang: A Fine-Grained Pipelined Implementation for Large-Scale Matrix Inversion on FPGA. APPT 2009: 110-122
6		Guiming Wu, Yong Dou, Yuanwu Lei, Jie Zhou, Miao Wang, Jingfei Jiang: A Fine-grained Pipelined Implementation of the LINPACK Benchmark on FPGAs. FCCM 2009: 183-190
5		Yong Dou, Jie Zhou, Xiaoyang Chen, Yuanwu Lei, Jinbo Xu: FPGA accelerating three QR decomposition algorithms in the unified pipelined framework. FPL 2009: 410-416
	2008
4		Jie Zhou, Yong Dou, Yuanwu Lei, Yazhuo Dong: Hybrid-Mode Floating-Point FPGA CORDIC Co-processor. ARC 2008: 254-259
3		Jie Zhou, Yong Dou, Yuanwu Lei, Jinbo Xu, Yazhuo Dong: Double Precision Hybrid-Mode Floating-Point FPGA CORDIC Co-processor. HPCC 2008: 182-189
2		Jie Zhou, Yazhuo Dong, Yong Dou, Yuanwu Lei: Dynamic Configurable Floating-Point FFT Pipelines and Hybrid-Mode CORDIC on FPGA. ICESS 2008: 616-620
	2007
1		Yong Dou, Jie Zhou, Yuanwu Lei, Xingming Zhou: FPGA SAR Processor with Window Memory Accesses. ASAP 2007: 95-100

Coauthor Index

1	Xiaoyang Chen	[5]
2	Yazhuo Dong	[2] [3] [4]
3	Yong Dou	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
4	Song Guo	[9] [11] [13] [14]
5	Jingfei Jiang	[6] [8]
6	Rongchun Li	[14]
7	Shi-Ce Ni	[8] [14]
8	Li Shen	[9] [11]
9	Yuxing Tang	[7]
10	Miao Wang	[6]
11	Sufeng Wang	[12]
12	Guiming Wu	[6] [8] [9]
13	Fei Xia	[7]
14	Jinbo Xu	[3] [5]
15	Jianxun Zhao	[7]
16	Jie Zhou	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
17	Xingming Zhou	[1]

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