 | 2011 |
| 14 |  | Dieter F. Wendel,
Ronald N. Kalla,
James D. Warnock,
Robert Cargnoni,
Sam G. Chu,
Joachim G. Clabes,
Daniel Dreps,
David Hrusecky,
Joshua Friedrich,
Md. Saiful Islam,
James A. Kahle,
Jens Leenstra,
Gaurav Mittal,
Jose Paredes,
Juergen Pille,
Phillip J. Restle,
Balaram Sinharoy,
George Smith,
William J. Starke,
Scott Taylor,
James Van Norstrand,
Stephen Weitzel,
Phillip G. Williams,
Victor V. Zyuban:
POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor.
J. Solid-State Circuits 46(1): 145-161 (2011) |
| 2008 |
| 13 |  | Melanie Elm,
Hans-Joachim Wunderlich,
Michael E. Imhof,
Christian G. Zoellin,
Jens Leenstra,
Nicolas Mäding:
Scan chain clustering for test power reduction.
DAC 2008: 828-833 |
| 2007 |
| 12 |  | Michael E. Imhof,
Christian G. Zoellin,
Hans-Joachim Wunderlich,
Nicolas Mäding,
Jens Leenstra:
Scan Test Planning for Power Reduction.
DAC 2007: 521-526 |
| 11 |  | Brian K. Flachs,
Shigehiro Asano,
Sang H. Dhong,
H. Peter Hofstee,
Gilles Gervais,
Roy Kim,
Tien Le,
Peichun Liu,
Jens Leenstra,
John S. Liberty,
Brad W. Michael,
Hwa-Joon Oh,
Silvia M. Müller,
Osamu Takahashi,
Koji Hirairi,
Atsushi Kawasumi,
Hiroaki Murakami,
Hiromi Noro,
Shoji Onishi,
Juergen Pille,
Joel Silberman,
Suksoon Yong,
Akiyuki Hatakeyama,
Yukio Watanabe,
Naoka Yano,
Daniel A. Brokenshire,
Mohammad Peyravian,
VanDung To,
Eiji Iwata:
Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI.
IBM Journal of Research and Development 51(5): 529-544 (2007) |
| 10 |  | Lee Eisen,
John Wesley Ward III,
Hans-Werner Tast,
Nicolas Mäding,
Jens Leenstra,
Silvia M. Müller,
Christian Jacobi,
Jochen Preiss,
Eric M. Schwarz,
Steven R. Carlough:
IBM POWER6 accelerators: VMX and DFU.
IBM Journal of Research and Development 51(6): 663-684 (2007) |
| 9 |  | Joachim Fenkes,
Tobias Gemmeke,
Jens Leenstra:
Efficiency of Low Power Circuit Techniques in a 65 nm SOI-Process.
J. Low Power Electronics 3(1): 54-59 (2007) |
| 2006 |
| 8 |  | Nicolas Mäding,
Jens Leenstra,
Juergen Pille,
Rolf Sautter,
Stefan Büttner,
S. Ehrenreich,
W. Haller:
The vector fixed point unit of the synergistic processor element of the cell architecture processor.
DATE Designers' Forum 2006: 244-248 |
| 7 |  | Christian G. Zoellin,
Hans-Joachim Wunderlich,
Nicolas Mäding,
Jens Leenstra:
BIST Power Reduction Using Scan-Chain Disable in the Cell Processor.
ITC 2006: 1-8 |
| 2001 |
| 6 |  | Michael Kessler,
Gundolf Kiefer,
Jens Leenstra,
Knut Schünemann,
Thomas Schwarz,
Hans-Joachim Wunderlich:
Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability.
ITC 2001: 461-469 |
| 2000 |
| 5 |  | David H. Allen,
Sang H. Dhong,
H. Peter Hofstee,
Jens Leenstra,
Kevin J. Nowka,
Daniel L. Stasiak,
Dieter F. Wendel:
Custom circuit design as a driver of microprocessor performance.
IBM Journal of Research and Development 44(6): 799-822 (2000) |
| 1997 |
| 4 |  | Jörg A. Walter,
Jens Leenstra,
Gerhard Döttling,
Bernd Leppla,
Hans-Jürgen Münster,
Kevin W. Kark,
Bruce Wile:
Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors.
DAC 1997: 89-94 |
| 1991 |
| 3 |  | Jens Leenstra,
Lambert Spaanenburg:
Hierarchical Test Program Development for Scan Testable Circuits.
ITC 1991: 375-384 |
| 1990 |
| 2 |  | Jens Leenstra,
Lambert Spaanenburg:
Hierarchical test assembly for macro based VLSI design.
ITC 1990: 520-529 |
| 1989 |
| 1 |  | Jens Leenstra,
Lambert Spaanenburg:
On the Design and Test of Asynchronous Macros Embedded in Synchronous Systems.
ITC 1989: 838-845 |