Yung-Pin Lee

	2011
14		Xuan-Lun Huang, Ping-Ying Kang, Hsiu-Ming Chang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai, Cheng-Wen Wu: A self-testing and calibration method for embedded successive approximation register ADC. ASP-DAC 2011: 713-718
13		Cihun-Siyong Alex Gong, Tim K. Shia, Yung-Pin Lee, Bo-Wei Chen, Kai-Wen Yao, Muh-Tian Shiue: CMOS comparator for medical imaging. BMEI 2011: 1060-1063
12		Xuan-Lun Huang, Ping-Ying Kang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai: A Pre- and Post-bond Self-Testing and Calibration Methodology for SAR ADC Array in 3-D CMOS Imager. European Test Symposium 2011: 39-44
11		Pingli Huang, Szukang Hsien, Victor Lu, Peiyuan Wan, Seung-Chul Lee, Wenbo Liu, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu: SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration. J. Solid-State Circuits 46(8): 1893-1903 (2011)
	2010
10		Pingli Huang, Szukang Hsien, Victor Lu, Peiyuan Wan, Seung-Chul Lee, Wenbo Liu, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu: SHA-less pipelined ADC converting 10th Nyquist band with in-situ clock-skew calibration. CICC 2010: 1-4
9		Ji-Eun Jang, Yung-Kuang Miao, Yung-Pin Lee: High-bandwidth power-scalable 10-bit pipelined ADC using bandwidth-reconfigurable operational amplifier. ISCAS 2010: 4029-4032
8		Kuan-Yu Lin, Ji-Eun Jang, Ching-Hsuan Hsieh, Yung-Pin Lee: A pipelined analog-to-digital converter using incomplete-settling-without-slewing technique. ISCAS 2010: 4037-4040
	2009
7		Wenbo Liu, Yuchun Chang, Szukang Hsien, Bo-Wei Chen, Yung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Yang, Gin-Kou Ma, Yun Chiu: A 600MS/s 30mW 0.13µm CMOS ADC array achieving over 60dB SFDR with adaptive digital equalization. ISSCC 2009: 82-83
6		Jri Lee, Huaide Wang, Wen-Tsao Chen, Yung-Pin Lee: Subharmonically injection-locked PLLs for ultra-low-noise clock generation. ISSCC 2009: 92-93
	2008
5		Chung-Wei Lin, Yung-Pin Lee, Wen-Tsao Chen: A 1.5 bit 5th order CT/DT delta sigma class D amplifier with power efficiency improvement. ISCAS 2008: 280-283
	2007
4		Huan-Jen Yang, Ke-Horng Chen, Yung-Pin Lee: Feed-Forward Pulse Width Modulation for High Line Regulation Buck or Boost Converters. ISCAS 2007: 785-788
	1998
3		Liang-Gee Chen, Juing-Ying Jiu, Hao-Chieh Chang, Yung-Pin Lee, Chung-Wei Ku: A Low Power 2-D DCT Chip Design Using Direct 2-D Algorithm. ASP-DAC 1998: 145-150
	1997
2		Yeong-Kang Lai, Liang-Gee Chen, Yung-Pin Lee: A flexible data-interlacing architecture for full-search block-matching algorithm. ASAP 1997: 96-
1		Yung-Pin Lee, Thou-Ho Chen, Liang-Gee Chen, Mei-Juan Chen, Chung-Wei Ku: A cost-effective architecture for 8×8 two-dimensional DCT/IDCT using direct method. IEEE Trans. Circuits Syst. Video Techn. 7(3): 459-467 (1997)

Coauthor Index

1	Hao-Chieh Chang	[3]
2	Hsiu-Ming Chang	[14]
3	Yuchun Chang	[7]
4	Bo-Wei Chen	[7] [10] [11] [13]
5	Chao-Ho Chen (Thou-Ho Chen)	[1]
6	Ke-Horng Chen	[4]
7	Liang-Gee Chen	[1] [2] [3]
8	Mei-Juan Chen	[1]
9	Wen-Tsao Chen	[5] [6] [7] [10] [11]
10	Yun Chiu	[7] [10] [11]
11	Yung-Fa Chou	[12] [14]
12	Cihun-Siyong Alex Gong	[13]
13	Ching-Hsuan Hsieh	[8]
14	Szukang Hsien	[7] [10] [11]
15	Jiun-Lang Huang	[12] [14]
16	Pingli Huang	[10] [11]
17	Xuan-Lun Huang	[12] [14]
18	Ji-Eun Jang	[8] [9]
19	Juing-Ying Jiu	[3]
20	Ping-Ying Kang	[12] [14]
21	Chung-Wei Ku	[1] [3]
22	Ding-Ming Kwai	[12] [14]
23	Yeong-Kang Lai	[2]
24	Jri Lee	[6]
25	Seung-Chul Lee	[10] [11]
26	Chung-Wei Lin	[5]
27	Kuan-Yu Lin	[8]
28	Wenbo Liu	[7] [10] [11]
29	Victor Lu	[10] [11]
30	Gin-Kou Ma	[7] [10] [11]
31	Yung-Kuang Miao	[9]
32	Tim K. Shia	[13]
33	Muh-Tian Shiue	[13]
34	Peiyuan Wan	[10] [11]
35	Huaide Wang	[6]
36	Cheng-Wen Wu	[14]
37	Huan-Jen Yang	[4]
38	Tzu-Yi Yang	[7] [10] [11]
39	Kai-Wen Yao	[13]

Colors in the list of coauthors

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